2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 static void setup_mb_resource_map(void)
24 static const unsigned int register_values[] = {
25 /* Careful set limit registers before base registers which contain the enables */
26 /* DRAM Limit i Registers
35 * [ 2: 0] Destination Node ID
45 * [10: 8] Interleave select
46 * specifies the values of A[14:12] to use with interleave enable.
48 * [31:16] DRAM Limit Address i Bits 39-24
49 * This field defines the upper address bits of a 40 bit address
50 * that define the end of the DRAM region.
52 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
53 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
54 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
55 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
56 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
57 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
58 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
59 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
60 /* DRAM Base i Registers
72 * [ 1: 1] Write Enable
76 * [10: 8] Interleave Enable
78 * 001 = Interleave on A[12] (2 nodes)
80 * 011 = Interleave on A[12] and A[14] (4 nodes)
84 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
86 * [13:16] DRAM Base Address i Bits 39-24
87 * This field defines the upper address bits of a 40-bit address
88 * that define the start of the DRAM region.
90 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
91 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
92 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
93 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
94 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
95 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
96 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
97 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
99 /* Memory-Mapped I/O Limit i Registers
108 * [ 2: 0] Destination Node ID
118 * [ 5: 4] Destination Link ID
125 * 0 = CPU writes may be posted
126 * 1 = CPU writes must be non-posted
127 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
128 * This field defines the upp adddress bits of a 40-bit address that
129 * defines the end of a memory-mapped I/O region n
131 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
132 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
133 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
134 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
135 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
136 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
137 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
138 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
140 /* Memory-Mapped I/O Base i Registers
149 * [ 0: 0] Read Enable
152 * [ 1: 1] Write Enable
153 * 0 = Writes disabled
155 * [ 2: 2] Cpu Disable
156 * 0 = Cpu can use this I/O range
157 * 1 = Cpu requests do not use this I/O range
159 * 0 = base/limit registers i are read/write
160 * 1 = base/limit registers i are read-only
162 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
163 * This field defines the upper address bits of a 40bit address
164 * that defines the start of memory-mapped I/O region i
166 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
167 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
168 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
169 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
170 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
171 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
172 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
173 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
175 /* PCI I/O Limit i Registers
180 * [ 2: 0] Destination Node ID
190 * [ 5: 4] Destination Link ID
196 * [24:12] PCI I/O Limit Address i
197 * This field defines the end of PCI I/O region n
200 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
201 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
202 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
203 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
205 /* PCI I/O Base i Registers
210 * [ 0: 0] Read Enable
213 * [ 1: 1] Write Enable
214 * 0 = Writes Disabled
218 * 0 = VGA matches Disabled
219 * 1 = matches all address < 64K and where A[9:0] is in the
220 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
222 * 0 = ISA matches Disabled
223 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
224 * from matching agains this base/limit pair
226 * [24:12] PCI I/O Base i
227 * This field defines the start of PCI I/O region n
230 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
231 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
232 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
233 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
235 /* Config Base and Limit i Registers
240 * [ 0: 0] Read Enable
243 * [ 1: 1] Write Enable
244 * 0 = Writes Disabled
246 * [ 2: 2] Device Number Compare Enable
247 * 0 = The ranges are based on bus number
248 * 1 = The ranges are ranges of devices on bus 0
250 * [ 6: 4] Destination Node
260 * [ 9: 8] Destination Link
266 * [23:16] Bus Number Base i
267 * This field defines the lowest bus number in configuration region i
268 * [31:24] Bus Number Limit i
269 * This field defines the highest bus number in configuration regin i
271 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
272 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
273 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
274 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
278 max = ARRAY_SIZE(register_values);
279 setup_resource_map(register_values, max);