2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <cpu/x86/msr.h>
25 #include <cpu/amd/mtrr.h>
26 #include <device/pci_def.h>
27 #include <southbridge/amd/sb700/sb700.h>
31 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
32 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
36 #define SMBUS_IO_BASE 0x6000
38 uint64_t uma_memory_base, uma_memory_size;
40 void set_pcie_dereset(void);
41 void set_pcie_reset(void);
42 u8 is_dev3_present(void);
44 void set_pcie_dereset()
49 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
50 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
51 byte = pm_ioread(0x8d);
52 byte &= ~((1 << 1) | (1 << 2));
53 pm_iowrite(0x8d, byte);
55 /* set the GPM8 and GPM9 output enable and the value to 1 */
56 byte = pm_ioread(0x94);
57 byte &= ~((1 << 2) | (1 << 3));
58 byte |= ((1 << 0) | (1 << 1));
59 pm_iowrite(0x94, byte);
61 /* set the GPIO65 output enable and the value is 1 */
62 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
63 word = pci_read_config16(sm_dev, 0x7e);
66 pci_write_config16(sm_dev, 0x7e, word);
75 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
76 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
77 byte = pm_ioread(0x8d);
78 byte &= ~((1 << 1) | (1 << 2));
79 pm_iowrite(0x8d, byte);
81 /* set the GPM8 and GPM9 output enable and the value to 0 */
82 byte = pm_ioread(0x94);
83 byte &= ~((1 << 2) | (1 << 3));
84 byte &= ~((1 << 0) | (1 << 1));
85 pm_iowrite(0x94, byte);
87 /* set the GPIO65 output enable and the value is 0 */
88 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
89 word = pci_read_config16(sm_dev, 0x7e);
92 pci_write_config16(sm_dev, 0x7e, word);
96 /********************************************************
97 * tilapia uses SB700 GPIO8 to detect IDE_DMA66.
98 * IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
99 * get the cable type, 40 pin or 80 pin?
100 ********************************************************/
101 static void get_ide_dma66(void)
104 /*u32 sm_dev, ide_dev; */
105 device_t sm_dev, ide_dev;
107 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
109 byte = pci_read_config8(sm_dev, 0xA9);
110 byte |= (1 << 4); /* Set Gpio8 as input */
111 pci_write_config8(sm_dev, 0xA9, byte);
113 ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
114 byte = pci_read_config8(ide_dev, 0x56);
116 if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
117 byte |= 2 << 0; /* mode 2 */
119 byte |= 5 << 0; /* mode 5 */
120 pci_write_config8(ide_dev, 0x56, byte);
125 * justify the dev3 is exist or not
126 * NOTE: This just copied from AMD Tilapia code.
127 * It is completly unknown if it will work at all for this board.
129 u8 is_dev3_present(void)
134 /* access the smbus extended register */
135 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
137 /* put the GPIO68 output to tristate */
138 word = pci_read_config16(sm_dev, 0x7e);
140 pci_write_config16(sm_dev, 0x7e,word);
142 /* read the GPIO68 input status */
143 word = pci_read_config16(sm_dev, 0x7e);
145 if(word & (1 << 10)){
155 /*************************************************
156 * enable the dedicated function in this board.
157 * This function called early than rs780_enable.
158 *************************************************/
159 static void m4a78em_enable(device_t dev)
161 printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
163 #if (CONFIG_GFXUMA == 1)
166 /* TOP_MEM: the top of DRAM below 4G */
167 msr = rdmsr(TOP_MEM);
169 "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
170 __func__, msr.lo, msr.hi);
172 /* TOP_MEM2: the top of DRAM above 4G */
173 msr2 = rdmsr(TOP_MEM2);
175 "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
176 __func__, msr2.lo, msr2.hi);
179 case 0x10000000: /* 256M system memory */
180 uma_memory_size = 0x4000000; /* 64M recommended UMA */
183 case 0x20000000: /* 512M system memory */
184 uma_memory_size = 0x8000000; /* 128M recommended UMA */
187 default: /* 1GB and above system memory */
188 uma_memory_size = 0x10000000; /* 256M recommended UMA */
192 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
193 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
194 __func__, uma_memory_size, uma_memory_base);
198 uma_memory_size = 0x8000000; /* 128M recommended UMA */
199 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
203 /* get_ide_dma66(); */
204 /* set_thermal_config(); */
207 struct chip_operations mainboard_ops = {
208 CHIP_NAME("ASUS M4A78-EM Mainboard")
209 .enable_dev = m4a78em_enable,