2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
26 "TILAPIA ", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
40 Name(HPBA, 0xFED00000) /* Base address of HPET table */
42 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44 /* USB overcurrent mapping pins. */
56 /* Some global data */
57 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
58 Name(OSV, Ones) /* Assume nothing */
59 Name(PMOD, One) /* Assume APIC */
65 Scope (\_PR) { /* define processor scope */
67 CPU0, /* name space name */
68 0, /* Unique number for this processor */
69 0x808, /* PBLK system I/O address !hardcoded! */
70 0x06 /* PBLKLEN for boot processor */
72 #include "acpi/cpstate.asl"
76 CPU1, /* name space name */
77 1, /* Unique number for this processor */
78 0x0000, /* PBLK system I/O address !hardcoded! */
79 0x00 /* PBLKLEN for boot processor */
81 #include "acpi/cpstate.asl"
85 CPU2, /* name space name */
86 2, /* Unique number for this processor */
87 0x0000, /* PBLK system I/O address !hardcoded! */
88 0x00 /* PBLKLEN for boot processor */
90 #include "acpi/cpstate.asl"
94 CPU3, /* name space name */
95 3, /* Unique number for this processor */
96 0x0000, /* PBLK system I/O address !hardcoded! */
97 0x00 /* PBLKLEN for boot processor */
99 #include "acpi/cpstate.asl"
101 } /* End _PR scope */
103 /* PIC IRQ mapping registers, C00h-C01h */
104 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
105 Field(PRQM, ByteAcc, NoLock, Preserve) {
107 PRQD, 0x00000008, /* Offset: 1h */
109 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
110 PINA, 0x00000008, /* Index 0 */
111 PINB, 0x00000008, /* Index 1 */
112 PINC, 0x00000008, /* Index 2 */
113 PIND, 0x00000008, /* Index 3 */
114 AINT, 0x00000008, /* Index 4 */
115 SINT, 0x00000008, /* Index 5 */
116 , 0x00000008, /* Index 6 */
117 AAUD, 0x00000008, /* Index 7 */
118 AMOD, 0x00000008, /* Index 8 */
119 PINE, 0x00000008, /* Index 9 */
120 PINF, 0x00000008, /* Index A */
121 PING, 0x00000008, /* Index B */
122 PINH, 0x00000008, /* Index C */
125 /* PCI Error control register */
126 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
127 Field(PERC, ByteAcc, NoLock, Preserve) {
134 /* Client Management index/data registers */
135 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
136 Field(CMT, ByteAcc, NoLock, Preserve) {
138 /* Client Management Data register */
146 /* GPM Port register */
147 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
148 Field(GPT, ByteAcc, NoLock, Preserve) {
159 /* Flash ROM program enable register */
160 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
161 Field(FRE, ByteAcc, NoLock, Preserve) {
166 /* PM2 index/data registers */
167 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
168 Field(PM2R, ByteAcc, NoLock, Preserve) {
173 /* Power Management I/O registers */
174 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
175 Field(PIOR, ByteAcc, NoLock, Preserve) {
179 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
180 Offset(0x00), /* MiscControl */
184 Offset(0x01), /* MiscStatus */
188 Offset(0x04), /* SmiWakeUpEventEnable3 */
191 Offset(0x07), /* SmiWakeUpEventStatus3 */
194 Offset(0x10), /* AcpiEnable */
197 Offset(0x1C), /* ProgramIoEnable */
204 Offset(0x1D), /* IOMonitorStatus */
211 Offset(0x20), /* AcpiPmEvtBlk */
213 Offset(0x36), /* GEvtLevelConfig */
217 Offset(0x37), /* GPMLevelConfig0 */
224 Offset(0x38), /* GPMLevelConfig1 */
231 Offset(0x3B), /* PMEStatus1 */
240 Offset(0x55), /* SoftPciRst */
248 /* Offset(0x61), */ /* Options_1 */
252 Offset(0x65), /* UsbPMControl */
255 Offset(0x68), /* MiscEnable68 */
259 Offset(0x92), /* GEVENTIN */
262 Offset(0x96), /* GPM98IN */
265 Offset(0x9A), /* EnhanceControl */
268 Offset(0xA8), /* PIO7654Enable */
273 Offset(0xA9), /* PIO7654Status */
281 * First word is PM1_Status, Second word is PM1_Enable
283 OperationRegion(P1EB, SystemIO, APEB, 0x04)
284 Field(P1EB, ByteAcc, NoLock, Preserve) {
309 /* PCIe Configuration Space for 16 busses */
310 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
311 Field(PCFG, ByteAcc, NoLock, Preserve) {
312 /* Byte offsets are computed using the following technique:
313 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
314 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
316 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
318 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
329 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
332 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
334 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
336 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
338 P92E, 1, /* Port92 decode enable */
341 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
342 Field(SB5, AnyAcc, NoLock, Preserve){
344 Offset(0x120), /* Port 0 Task file status */
350 Offset(0x128), /* Port 0 Serial ATA status */
354 Offset(0x12C), /* Port 0 Serial ATA control */
356 Offset(0x130), /* Port 0 Serial ATA error */
361 offset(0x1A0), /* Port 1 Task file status */
367 Offset(0x1A8), /* Port 1 Serial ATA status */
371 Offset(0x1AC), /* Port 1 Serial ATA control */
373 Offset(0x1B0), /* Port 1 Serial ATA error */
378 Offset(0x220), /* Port 2 Task file status */
384 Offset(0x228), /* Port 2 Serial ATA status */
388 Offset(0x22C), /* Port 2 Serial ATA control */
390 Offset(0x230), /* Port 2 Serial ATA error */
395 Offset(0x2A0), /* Port 3 Task file status */
401 Offset(0x2A8), /* Port 3 Serial ATA status */
405 Offset(0x2AC), /* Port 3 Serial ATA control */
407 Offset(0x2B0), /* Port 3 Serial ATA error */
414 #include "acpi/routing.asl"
420 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
422 if(CondRefOf(\_OSI,Local1))
424 Store(1, OSTP) /* Assume some form of XP */
425 if (\_OSI("Windows 2006")) /* Vista */
430 If(WCMP(\_OS,"Linux")) {
431 Store(3, OSTP) /* Linux */
433 Store(4, OSTP) /* Gotta be WinCE */
439 Method(_PIC, 0x01, NotSerialized)
447 Method(CIRQ, 0x00, NotSerialized){
458 Name(IRQB, ResourceTemplate(){
459 IRQ(Level,ActiveLow,Shared){15}
462 Name(IRQP, ResourceTemplate(){
463 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
466 Name(PITF, ResourceTemplate(){
467 IRQ(Level,ActiveLow,Exclusive){9}
471 Name(_HID, EISAID("PNP0C0F"))
476 Return(0x0B) /* sata is invisible */
478 Return(0x09) /* sata is disabled */
480 } /* End Method(_SB.INTA._STA) */
483 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
485 } /* End Method(_SB.INTA._DIS) */
488 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
490 } /* Method(_SB.INTA._PRS) */
493 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
494 CreateWordField(IRQB, 0x1, IRQN)
495 ShiftLeft(1, PINA, IRQN)
497 } /* Method(_SB.INTA._CRS) */
500 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
501 CreateWordField(ARG0, 1, IRQM)
503 /* Use lowest available IRQ */
504 FindSetRightBit(IRQM, Local0)
509 } /* End Method(_SB.INTA._SRS) */
510 } /* End Device(INTA) */
513 Name(_HID, EISAID("PNP0C0F"))
518 Return(0x0B) /* sata is invisible */
520 Return(0x09) /* sata is disabled */
522 } /* End Method(_SB.INTB._STA) */
525 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
527 } /* End Method(_SB.INTB._DIS) */
530 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
532 } /* Method(_SB.INTB._PRS) */
535 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
536 CreateWordField(IRQB, 0x1, IRQN)
537 ShiftLeft(1, PINB, IRQN)
539 } /* Method(_SB.INTB._CRS) */
542 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
543 CreateWordField(ARG0, 1, IRQM)
545 /* Use lowest available IRQ */
546 FindSetRightBit(IRQM, Local0)
551 } /* End Method(_SB.INTB._SRS) */
552 } /* End Device(INTB) */
555 Name(_HID, EISAID("PNP0C0F"))
560 Return(0x0B) /* sata is invisible */
562 Return(0x09) /* sata is disabled */
564 } /* End Method(_SB.INTC._STA) */
567 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
569 } /* End Method(_SB.INTC._DIS) */
572 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
574 } /* Method(_SB.INTC._PRS) */
577 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
578 CreateWordField(IRQB, 0x1, IRQN)
579 ShiftLeft(1, PINC, IRQN)
581 } /* Method(_SB.INTC._CRS) */
584 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
585 CreateWordField(ARG0, 1, IRQM)
587 /* Use lowest available IRQ */
588 FindSetRightBit(IRQM, Local0)
593 } /* End Method(_SB.INTC._SRS) */
594 } /* End Device(INTC) */
597 Name(_HID, EISAID("PNP0C0F"))
602 Return(0x0B) /* sata is invisible */
604 Return(0x09) /* sata is disabled */
606 } /* End Method(_SB.INTD._STA) */
609 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
611 } /* End Method(_SB.INTD._DIS) */
614 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
616 } /* Method(_SB.INTD._PRS) */
619 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
620 CreateWordField(IRQB, 0x1, IRQN)
621 ShiftLeft(1, PIND, IRQN)
623 } /* Method(_SB.INTD._CRS) */
626 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
627 CreateWordField(ARG0, 1, IRQM)
629 /* Use lowest available IRQ */
630 FindSetRightBit(IRQM, Local0)
635 } /* End Method(_SB.INTD._SRS) */
636 } /* End Device(INTD) */
639 Name(_HID, EISAID("PNP0C0F"))
644 Return(0x0B) /* sata is invisible */
646 Return(0x09) /* sata is disabled */
648 } /* End Method(_SB.INTE._STA) */
651 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
653 } /* End Method(_SB.INTE._DIS) */
656 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
658 } /* Method(_SB.INTE._PRS) */
661 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
662 CreateWordField(IRQB, 0x1, IRQN)
663 ShiftLeft(1, PINE, IRQN)
665 } /* Method(_SB.INTE._CRS) */
668 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
669 CreateWordField(ARG0, 1, IRQM)
671 /* Use lowest available IRQ */
672 FindSetRightBit(IRQM, Local0)
677 } /* End Method(_SB.INTE._SRS) */
678 } /* End Device(INTE) */
681 Name(_HID, EISAID("PNP0C0F"))
686 Return(0x0B) /* sata is invisible */
688 Return(0x09) /* sata is disabled */
690 } /* End Method(_SB.INTF._STA) */
693 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
695 } /* End Method(_SB.INTF._DIS) */
698 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
700 } /* Method(_SB.INTF._PRS) */
703 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
704 CreateWordField(IRQB, 0x1, IRQN)
705 ShiftLeft(1, PINF, IRQN)
707 } /* Method(_SB.INTF._CRS) */
710 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
711 CreateWordField(ARG0, 1, IRQM)
713 /* Use lowest available IRQ */
714 FindSetRightBit(IRQM, Local0)
719 } /* End Method(_SB.INTF._SRS) */
720 } /* End Device(INTF) */
723 Name(_HID, EISAID("PNP0C0F"))
728 Return(0x0B) /* sata is invisible */
730 Return(0x09) /* sata is disabled */
732 } /* End Method(_SB.INTG._STA) */
735 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
737 } /* End Method(_SB.INTG._DIS) */
740 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
742 } /* Method(_SB.INTG._CRS) */
745 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
746 CreateWordField(IRQB, 0x1, IRQN)
747 ShiftLeft(1, PING, IRQN)
749 } /* Method(_SB.INTG._CRS) */
752 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
753 CreateWordField(ARG0, 1, IRQM)
755 /* Use lowest available IRQ */
756 FindSetRightBit(IRQM, Local0)
761 } /* End Method(_SB.INTG._SRS) */
762 } /* End Device(INTG) */
765 Name(_HID, EISAID("PNP0C0F"))
770 Return(0x0B) /* sata is invisible */
772 Return(0x09) /* sata is disabled */
774 } /* End Method(_SB.INTH._STA) */
777 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
779 } /* End Method(_SB.INTH._DIS) */
782 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
784 } /* Method(_SB.INTH._CRS) */
787 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
788 CreateWordField(IRQB, 0x1, IRQN)
789 ShiftLeft(1, PINH, IRQN)
791 } /* Method(_SB.INTH._CRS) */
794 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
795 CreateWordField(ARG0, 1, IRQM)
797 /* Use lowest available IRQ */
798 FindSetRightBit(IRQM, Local0)
803 } /* End Method(_SB.INTH._SRS) */
804 } /* End Device(INTH) */
806 } /* End Scope(_SB) */
809 /* Supported sleep states: */
810 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
812 If (LAnd(SSFG, 0x01)) {
813 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
815 If (LAnd(SSFG, 0x02)) {
816 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
818 If (LAnd(SSFG, 0x04)) {
819 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
821 If (LAnd(SSFG, 0x08)) {
822 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
825 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
827 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
828 Name(CSMS, 0) /* Current System State */
830 /* Wake status package */
831 Name(WKST,Package(){Zero, Zero})
834 * \_PTS - Prepare to Sleep method
837 * Arg0=The value of the sleeping state S1=1, S2=2, etc
842 * The _PTS control method is executed at the beginning of the sleep process
843 * for S1-S5. The sleeping value is passed to the _PTS control method. This
844 * control method may be executed a relatively long time before entering the
845 * sleep state and the OS may abort the operation without notification to
846 * the ACPI driver. This method cannot modify the configuration or power
847 * state of any device in the system.
850 /* DBGO("\\_PTS\n") */
851 /* DBGO("From S0 to S") */
855 /* Don't allow PCIRST# to reset USB */
860 /* Clear sleep SMI status flag and enable sleep SMI trap. */
864 /* On older chips, clear PciExpWakeDisEn */
865 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
870 /* Clear wake status structure. */
871 Store(0, Index(WKST,0))
872 Store(0, Index(WKST,1))
873 \_SB.PCI0.SIOS (Arg0)
874 } /* End Method(\_PTS) */
877 * The following method results in a "not a valid reserved NameSeg"
878 * warning so I have commented it out for the duration. It isn't
879 * used, so it could be removed.
882 * \_GTS OEM Going To Sleep method
885 * Arg0=The value of the sleeping state S1=1, S2=2
892 * DBGO("From S0 to S")
899 * \_BFS OEM Back From Sleep method
902 * Arg0=The value of the sleeping state S1=1, S2=2
908 /* DBGO("\\_BFS\n") */
911 /* DBGO(" to S0\n") */
915 * \_WAK System Wake method
918 * Arg0=The value of the sleeping state S1=1, S2=2
921 * Return package of 2 DWords
923 * 0x00000000 wake succeeded
924 * 0x00000001 Wake was signaled but failed due to lack of power
925 * 0x00000002 Wake was signaled but failed due to thermal condition
926 * Dword 2 - Power Supply state
927 * if non-zero the effective S-state the power supply entered
930 /* DBGO("\\_WAK\n") */
933 /* DBGO(" to S0\n") */
938 /* Restore PCIRST# so it resets USB */
943 /* Arbitrarily clear PciExpWakeStatus */
946 /* if(DeRefOf(Index(WKST,0))) {
947 * Store(0, Index(WKST,1))
949 * Store(Arg0, Index(WKST,1))
952 \_SB.PCI0.SIOW (Arg0)
954 } /* End Method(\_WAK) */
956 Scope(\_GPE) { /* Start Scope GPE */
957 /* General event 0 */
959 * DBGO("\\_GPE\\_L00\n")
963 /* General event 1 */
965 * DBGO("\\_GPE\\_L00\n")
969 /* General event 2 */
971 * DBGO("\\_GPE\\_L00\n")
975 /* General event 3 */
977 /* DBGO("\\_GPE\\_L00\n") */
978 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
981 /* General event 4 */
983 * DBGO("\\_GPE\\_L00\n")
987 /* General event 5 */
989 * DBGO("\\_GPE\\_L00\n")
993 /* General event 6 - Used for GPM6, moved to USB.asl */
995 * DBGO("\\_GPE\\_L00\n")
999 /* General event 7 - Used for GPM7, moved to USB.asl */
1001 * DBGO("\\_GPE\\_L07\n")
1005 /* Legacy PM event */
1007 /* DBGO("\\_GPE\\_L08\n") */
1010 /* Temp warning (TWarn) event */
1012 /* DBGO("\\_GPE\\_L09\n") */
1013 Notify (\_TZ.TZ00, 0x80)
1018 * DBGO("\\_GPE\\_L0A\n")
1022 /* USB controller PME# */
1024 /* DBGO("\\_GPE\\_L0B\n") */
1025 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1026 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1027 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1028 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1029 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1030 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1031 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1034 /* AC97 controller PME# */
1036 * DBGO("\\_GPE\\_L0C\n")
1040 /* OtherTherm PME# */
1042 * DBGO("\\_GPE\\_L0D\n")
1046 /* GPM9 SCI event - Moved to USB.asl */
1048 * DBGO("\\_GPE\\_L0E\n")
1052 /* PCIe HotPlug event */
1054 * DBGO("\\_GPE\\_L0F\n")
1058 /* ExtEvent0 SCI event */
1060 /* DBGO("\\_GPE\\_L10\n") */
1064 /* ExtEvent1 SCI event */
1066 /* DBGO("\\_GPE\\_L11\n") */
1069 /* PCIe PME# event */
1071 * DBGO("\\_GPE\\_L12\n")
1075 /* GPM0 SCI event - Moved to USB.asl */
1077 * DBGO("\\_GPE\\_L13\n")
1081 /* GPM1 SCI event - Moved to USB.asl */
1083 * DBGO("\\_GPE\\_L14\n")
1087 /* GPM2 SCI event - Moved to USB.asl */
1089 * DBGO("\\_GPE\\_L15\n")
1093 /* GPM3 SCI event - Moved to USB.asl */
1095 * DBGO("\\_GPE\\_L16\n")
1099 /* GPM8 SCI event - Moved to USB.asl */
1101 * DBGO("\\_GPE\\_L17\n")
1105 /* GPIO0 or GEvent8 event */
1107 /* DBGO("\\_GPE\\_L18\n") */
1108 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1109 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1110 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1111 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1112 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1113 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1116 /* GPM4 SCI event - Moved to USB.asl */
1118 * DBGO("\\_GPE\\_L19\n")
1122 /* GPM5 SCI event - Moved to USB.asl */
1124 * DBGO("\\_GPE\\_L1A\n")
1128 /* Azalia SCI event */
1130 /* DBGO("\\_GPE\\_L1B\n") */
1131 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1132 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1135 /* GPM6 SCI event - Reassigned to _L06 */
1137 * DBGO("\\_GPE\\_L1C\n")
1141 /* GPM7 SCI event - Reassigned to _L07 */
1143 * DBGO("\\_GPE\\_L1D\n")
1147 /* GPIO2 or GPIO66 SCI event */
1149 * DBGO("\\_GPE\\_L1E\n")
1153 /* SATA SCI event - Moved to sata.asl */
1155 * DBGO("\\_GPE\\_L1F\n")
1159 } /* End Scope GPE */
1161 #include "acpi/usb.asl"
1164 Scope(\_SB) { /* Start \_SB scope */
1165 #include "../../../arch/i386/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1168 /* Note: Only need HID on Primary Bus */
1171 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1172 Name(_HID, EISAID("PNP0A03"))
1173 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1174 Method(_BBN, 0) { /* Bus number = 0 */
1178 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1179 Return(0x0B) /* Status is visible */
1183 If(PMOD){ Return(APR0) } /* APIC mode */
1184 Return (PR0) /* PIC Mode */
1187 /* Describe the Northbridge devices */
1189 Name(_ADR, 0x00000000)
1192 /* The internal GFX bridge */
1194 Name(_ADR, 0x00010000)
1195 Name(_PRW, Package() {0x18, 4})
1201 /* The external GFX bridge */
1203 Name(_ADR, 0x00020000)
1204 Name(_PRW, Package() {0x18, 4})
1206 If(PMOD){ Return(APS2) } /* APIC mode */
1207 Return (PS2) /* PIC Mode */
1211 /* Dev3 is also an external GFX bridge, not used in Herring */
1214 Name(_ADR, 0x00040000)
1215 Name(_PRW, Package() {0x18, 4})
1217 If(PMOD){ Return(APS4) } /* APIC mode */
1218 Return (PS4) /* PIC Mode */
1223 Name(_ADR, 0x00050000)
1224 Name(_PRW, Package() {0x18, 4})
1226 If(PMOD){ Return(APS5) } /* APIC mode */
1227 Return (PS5) /* PIC Mode */
1232 Name(_ADR, 0x00060000)
1233 Name(_PRW, Package() {0x18, 4})
1235 If(PMOD){ Return(APS6) } /* APIC mode */
1236 Return (PS6) /* PIC Mode */
1240 /* The onboard EtherNet chip */
1242 Name(_ADR, 0x00070000)
1243 Name(_PRW, Package() {0x18, 4})
1245 If(PMOD){ Return(APS7) } /* APIC mode */
1246 Return (PS7) /* PIC Mode */
1252 Name(_ADR, 0x00090000)
1253 Name(_PRW, Package() {0x18, 4})
1255 If(PMOD){ Return(APS9) } /* APIC mode */
1256 Return (PS9) /* PIC Mode */
1261 Name(_ADR, 0x000A0000)
1262 Name(_PRW, Package() {0x18, 4})
1264 If(PMOD){ Return(APSa) } /* APIC mode */
1265 Return (PSa) /* PIC Mode */
1270 /* PCI slot 1, 2, 3 */
1272 Name(_ADR, 0x00140004)
1273 Name(_PRW, Package() {0x18, 4})
1280 /* Describe the Southbridge devices */
1282 Name(_ADR, 0x00110000)
1283 #include "acpi/sata.asl"
1287 Name(_ADR, 0x00130000)
1288 Name(_PRW, Package() {0x0B, 3})
1292 Name(_ADR, 0x00130001)
1293 Name(_PRW, Package() {0x0B, 3})
1297 Name(_ADR, 0x00130002)
1298 Name(_PRW, Package() {0x0B, 3})
1302 Name(_ADR, 0x00130003)
1303 Name(_PRW, Package() {0x0B, 3})
1307 Name(_ADR, 0x00130004)
1308 Name(_PRW, Package() {0x0B, 3})
1312 Name(_ADR, 0x00130005)
1313 Name(_PRW, Package() {0x0B, 3})
1317 Name(_ADR, 0x00140000)
1320 /* Primary (and only) IDE channel */
1322 Name(_ADR, 0x00140001)
1323 #include "acpi/ide.asl"
1327 Name(_ADR, 0x00140002)
1328 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1329 Field(AZPD, AnyAcc, NoLock, Preserve) {
1353 If(LEqual(OSTP,3)){ /* If we are running Linux */
1362 Name(_ADR, 0x00140003)
1364 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1365 } */ /* End Method(_SB.SBRDG._INI) */
1367 /* Real Time Clock Device */
1369 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1370 Name(_CRS, ResourceTemplate() {
1372 IO(Decode16,0x0070, 0x0070, 0, 2)
1373 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1375 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1377 Device(TMR) { /* Timer */
1378 Name(_HID,EISAID("PNP0100")) /* System Timer */
1379 Name(_CRS, ResourceTemplate() {
1381 IO(Decode16, 0x0040, 0x0040, 0, 4)
1382 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1384 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1386 Device(SPKR) { /* Speaker */
1387 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1388 Name(_CRS, ResourceTemplate() {
1389 IO(Decode16, 0x0061, 0x0061, 0, 1)
1391 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1394 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1395 Name(_CRS, ResourceTemplate() {
1397 IO(Decode16,0x0020, 0x0020, 0, 2)
1398 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1399 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1400 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1402 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1404 Device(MAD) { /* 8257 DMA */
1405 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1406 Name(_CRS, ResourceTemplate() {
1407 DMA(Compatibility,BusMaster,Transfer8){4}
1408 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1409 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1410 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1411 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1412 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1413 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1414 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1415 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1418 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1419 Name(_CRS, ResourceTemplate() {
1420 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1423 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1426 Name(_HID,EISAID("PNP0103"))
1427 Name(CRS,ResourceTemplate() {
1428 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1431 Return(0x0F) /* sata is visible */
1434 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1438 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1442 Name(_ADR, 0x00140004)
1443 } /* end HostPciBr */
1446 Name(_ADR, 0x00140005)
1447 } /* end Ac97audio */
1450 Name(_ADR, 0x00140006)
1451 } /* end Ac97modem */
1453 /* ITE8718 Support */
1454 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1455 Field (IOID, ByteAcc, NoLock, Preserve)
1457 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1460 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1463 LDN, 8, /* Logical Device Number */
1465 CID1, 8, /* Chip ID Byte 1, 0x87 */
1466 CID2, 8, /* Chip ID Byte 2, 0x12 */
1468 ACTR, 8, /* Function activate */
1470 APC0, 8, /* APC/PME Event Enable Register */
1471 APC1, 8, /* APC/PME Status Register */
1472 APC2, 8, /* APC/PME Control Register 1 */
1473 APC3, 8, /* Environment Controller Special Configuration Register */
1474 APC4, 8 /* APC/PME Control Register 2 */
1477 /* Enter the 8718 MB PnP Mode */
1483 Store(0x55, SIOI) /* 8718 magic number */
1485 /* Exit the 8718 MB PnP Mode */
1492 * Keyboard PME is routed to SB700 Gevent3. We can wake
1493 * up the system by pressing the key.
1497 /* We only enable KBD PME for S5. */
1498 If (LLess (Arg0, 0x05))
1501 /* DBGO("8718F\n") */
1504 Store (One, ACTR) /* Enable EC */
1508 */ /* falling edge. which mode? Not sure. */
1511 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1513 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1522 Store (Zero, APC0) /* disable keyboard PME */
1524 Store (0xFF, APC1) /* clear keyboard PME status */
1528 Name(CRES, ResourceTemplate() {
1529 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1531 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1532 0x0000, /* address granularity */
1533 0x0000, /* range minimum */
1534 0x0CF7, /* range maximum */
1535 0x0000, /* translation */
1539 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1540 0x0000, /* address granularity */
1541 0x0D00, /* range minimum */
1542 0xFFFF, /* range maximum */
1543 0x0000, /* translation */
1547 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1548 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1549 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1550 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1552 /* DRAM Memory from 1MB to TopMem */
1553 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1555 /* BIOS space just below 4GB */
1557 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1558 0x00, /* Granularity */
1559 0x00000000, /* Min */
1560 0x00000000, /* Max */
1561 0x00000000, /* Translation */
1562 0x00000001, /* Max-Min, RLEN */
1567 /* DRAM memory from 4GB to TopMem2 */
1568 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1569 0x00000000, /* Granularity */
1570 0x00000000, /* Min */
1571 0x00000000, /* Max */
1572 0x00000000, /* Translation */
1573 0x00000001, /* Max-Min, RLEN */
1578 /* BIOS space just below 16EB */
1579 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1580 0x00000000, /* Granularity */
1581 0x00000000, /* Min */
1582 0x00000000, /* Max */
1583 0x00000000, /* Translation */
1584 0x00000001, /* Max-Min, RLEN */
1589 }) /* End Name(_SB.PCI0.CRES) */
1592 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1594 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1595 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1596 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1597 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1598 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1599 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1601 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1602 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1603 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1604 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1606 If(LGreater(LOMH, 0xC0000)){
1607 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1608 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1611 /* Set size of memory from 1MB to TopMem */
1612 Subtract(TOM1, 0x100000, DMLL)
1615 * If(LNotEqual(TOM2, 0x00000000)){
1616 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1617 * ShiftLeft(TOM2, 20, Local0)
1618 * Subtract(Local0, 0x100000000, DMHL)
1622 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1623 If(LEqual(TOM2, 0x00000000)){
1624 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1627 Else { /* Otherwise, put the BIOS just below 16EB */
1628 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1632 Return(CRES) /* note to change the Name buffer */
1633 } /* end of Method(_SB.PCI0._CRS) */
1637 * FIRST METHOD CALLED UPON BOOT
1639 * 1. If debugging, print current OS and ACPI interpreter.
1640 * 2. Get PCI Interrupt routing from ACPI VSM, this
1641 * value is based on user choice in BIOS setup.
1644 /* DBGO("\\_SB\\_INI\n") */
1645 /* DBGO(" DSDT.ASL code from ") */
1646 /* DBGO(__DATE__) */
1648 /* DBGO(__TIME__) */
1649 /* DBGO("\n Sleep states supported: ") */
1651 /* DBGO(" \\_OS=") */
1653 /* DBGO("\n \\_REV=") */
1657 /* Determine the OS we're running on */
1660 /* On older chips, clear PciExpWakeDisEn */
1661 /*if (LLessEqual(\SBRI, 0x13)) {
1665 } /* End Method(_SB._INI) */
1666 } /* End Device(PCI0) */
1668 Device(PWRB) { /* Start Power button device */
1669 Name(_HID, EISAID("PNP0C0C"))
1671 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1672 Name(_STA, 0x0B) /* sata is invisible */
1674 } /* End \_SB scope */
1678 /* DBGO("\\_SI\\_SST\n") */
1679 /* DBGO(" New Indicator state: ") */
1683 } /* End Scope SI */
1687 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1688 Field (SMB0, ByteAcc, NoLock, Preserve) {
1689 HSTS, 8, /* SMBUS status */
1690 SSTS, 8, /* SMBUS slave status */
1691 HCNT, 8, /* SMBUS control */
1692 HCMD, 8, /* SMBUS host cmd */
1693 HADD, 8, /* SMBUS address */
1694 DAT0, 8, /* SMBUS data0 */
1695 DAT1, 8, /* SMBUS data1 */
1696 BLKD, 8, /* SMBUS block data */
1697 SCNT, 8, /* SMBUS slave control */
1698 SCMD, 8, /* SMBUS shaow cmd */
1699 SEVT, 8, /* SMBUS slave event */
1700 SDAT, 8 /* SMBUS slave data */
1703 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1705 Store (0xFA, Local0)
1706 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1714 Method (SWTC, 1, NotSerialized) {
1715 Store (Arg0, Local0)
1716 Store (0x07, Local2)
1718 While (LEqual (Local1, One)) {
1719 Store (And (HSTS, 0x1E), Local3)
1720 If (LNotEqual (Local3, Zero)) { /* read sucess */
1721 If (LEqual (Local3, 0x02)) {
1722 Store (Zero, Local2)
1725 Store (Zero, Local1)
1728 If (LLess (Local0, 0x0A)) { /* read failure */
1729 Store (0x10, Local2)
1730 Store (Zero, Local1)
1733 Sleep (0x0A) /* 10 ms, try again */
1734 Subtract (Local0, 0x0A, Local0)
1742 Method (SMBR, 3, NotSerialized) {
1743 Store (0x07, Local0)
1744 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1745 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1746 If (LEqual (Local0, Zero)) {
1752 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1754 If (LEqual (Arg0, 0x07)) {
1755 Store (0x48, HCNT) /* read byte */
1758 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1759 If (LEqual (Local1, Zero)) {
1760 If (LEqual (Arg0, 0x07)) {
1761 Store (DAT0, Local0)
1765 Store (Local1, Local0)
1771 /* DBGO("the value of SMBusData0 register ") */
1787 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1788 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1789 Return(Add(0, 2730))
1791 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1792 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1793 Return(Package() {\_TZ.TZ00.FAN0})
1796 Name(_HID, EISAID("PNP0C0B"))
1797 Name(_PR0, Package() {PFN0})
1800 PowerResource(PFN0,0,0) {
1806 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1809 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1813 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1814 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1815 Return (Add (THOT, KELV))
1817 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1818 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1819 Return (Add (TCRT, KELV))
1821 Method(_TMP,0) { /* return current temp of this zone */
1822 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1823 If (LGreater (Local0, 0x10)) {
1824 Store (Local0, Local1)
1827 Add (Local0, THOT, Local0)
1828 Return (Add (400, KELV))
1831 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1832 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1833 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1834 If (LGreater (Local0, 0x10)) {
1835 If (LGreater (Local0, Local1)) {
1836 Store (Local0, Local1)
1839 Multiply (Local1, 10, Local1)
1840 Return (Add (Local1, KELV))
1843 Add (Local0, THOT, Local0)
1844 Return (Add (400 , KELV))
1850 /* End of ASL file */