2 * This file is part of the coreboot project.
4 * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
5 * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
7 * ISA portions taken from QEMU acpi-dsdt.dsl.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License v2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
25 Include ("amdk8_util.asl")
28 /* Define the main processor.*/
31 Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
32 Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
35 /* For now only define 2 power states:
36 * - S0 which is fully on
37 * - S5 which is soft off
38 * Any others would involve declaring the wake up methods.
40 Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
41 Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
43 /* Root of the bus hierarchy */
49 Name (_HID, EisaId ("PNP0A03"))
63 Method (_CRS, 0, NotSerialized)
65 Name (BUF0, ResourceTemplate ()
68 0x0CF8, // Address Range Minimum
69 0x0CF8, // Address Range Maximum
70 0x01, // Address Alignment
71 0x08, // Address Length
73 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
74 0x0000, // Address Space Granularity
75 0x0000, // Address Range Minimum
76 0x0CF7, // Address Range Maximum
77 0x0000, // Address Translation Offset
78 0x0CF8, // Address Length
81 /* Methods bellow use SSDT to get actual MMIO regs
82 The IO ports are from 0xd00, optionally an VGA,
83 otherwise the info from MMIO is used.
85 Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
86 Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
87 Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
91 /* PCI Routing Table */
92 Name (_PRT, Package () {
93 Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
94 Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
95 Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
96 Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
97 Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
98 Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
99 Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 }, /* LAN */
100 Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, /* PCIe bridge SB */
101 Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */
102 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */
103 Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */
104 Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
105 Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
106 Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
107 Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
108 Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
109 Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
110 Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
111 Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
116 Name (_ADR, 0x00020000)
119 Name (_PRT, Package () {
120 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
121 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
122 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
123 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
129 Name (_ADR, 0x00030000)
132 Name (_PRT, Package () {
133 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
134 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
135 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
136 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
142 Name (_ADR, 0x00130000)
145 Name (_PRT, Package () {
146 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* PCIE audio */
147 Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
148 Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x11 },
149 Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x11 },
155 Name (_ADR, 0x00130001)
158 Name (_PRT, Package () {
159 Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI slot */
160 Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
161 Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
162 Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
163 Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI slot */
164 Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
165 Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
166 Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
170 Name (_ADR, 0x00110000)
172 /* PS/2 keyboard (seems to be important for WinXP install) */
175 Name (_HID, EisaId ("PNP0303"))
176 Method (_STA, 0, NotSerialized)
180 Method (_CRS, 0, NotSerialized)
182 Name (TMP, ResourceTemplate () {
183 IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
184 IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
194 Name (_HID, EisaId ("PNP0F13"))
195 Method (_STA, 0, NotSerialized)
199 Method (_CRS, 0, NotSerialized)
201 Name (TMP, ResourceTemplate () {
208 /* PS/2 floppy controller */
211 Name (_HID, EisaId ("PNP0700"))
212 Method (_STA, 0, NotSerialized)
216 Method (_CRS, 0, NotSerialized)
218 Name (BUF0, ResourceTemplate () {
219 IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
220 IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
222 DMA (Compatibility, NotBusMaster, Transfer8) {2}