2 * This file is part of the coreboot project.
4 * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
5 * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
7 * ISA portions taken from QEMU acpi-dsdt.dsl.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License v2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
25 #include "northbridge/amd/amdk8/amdk8_util.asl"
27 /* For now only define 2 power states:
28 * - S0 which is fully on
29 * - S5 which is soft off
30 * Any others would involve declaring the wake up methods.
32 Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
33 Name (\_S3, Package () { 0x01, 0x01, 0x00, 0x00 })
34 Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
37 /* blink a LED when entering the sleep (any type) */
38 Method (_PTS, 1, NotSerialized)
40 Store (0x1, \_SB.PCI0.ISA.LEDR)
43 /* cancel a LED blinking when waking from sleep (any type) */
44 Method (_WAK, 1, NotSerialized)
46 Store (0x0, \_SB.PCI0.ISA.LEDR)
48 Return(Package(0x02){0x00, 0x00})
51 /* Root of the bus hierarchy */
57 Name (_HID, EisaId ("PNP0A03"))
71 Method (_CRS, 0, NotSerialized)
73 Name (BUF0, ResourceTemplate ()
76 0x0CF8, // Address Range Minimum
77 0x0CF8, // Address Range Maximum
78 0x01, // Address Alignment
79 0x08, // Address Length
81 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
82 0x0000, // Address Space Granularity
83 0x0000, // Address Range Minimum
84 0x0CF7, // Address Range Maximum
85 0x0000, // Address Translation Offset
86 0x0CF8, // Address Length
89 /* Methods bellow use SSDT to get actual MMIO regs
90 The IO ports are from 0xd00, optionally an VGA,
91 otherwise the info from MMIO is used.
93 Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
94 Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
95 Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
99 /* PCI Routing Table */
100 Name (_PRT, Package () {
101 Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
102 Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
103 Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
104 Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
105 Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
106 Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
107 Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 }, /* LAN */
108 Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, /* PCIe bridge SB */
109 Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */
110 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */
111 Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */
112 Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
113 Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
114 Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
115 Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
116 Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
117 Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
118 Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
119 Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
124 Name (_ADR, 0x00020000)
127 Name (_PRT, Package () {
128 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
129 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
130 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
131 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
137 Name (_ADR, 0x00030000)
140 Name (_PRT, Package () {
141 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
142 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
143 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
144 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
150 Name (_ADR, 0x00130000)
153 Name (_PRT, Package () {
154 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* PCIE audio */
155 Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
156 Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x11 },
157 Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x11 },
163 Name (_ADR, 0x00130001)
166 Name (_PRT, Package () {
167 Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI slot */
168 Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
169 Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
170 Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
171 Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI slot */
172 Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
173 Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
174 Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
178 Name (_ADR, 0x00110000)
179 OperationRegion (PCIC, PCI_Config, 0x0, 0xff)
180 Field (PCIC, ByteAcc, NoLock, Preserve)
183 /* two LSB bits are blink rate */
187 /* PS/2 keyboard (seems to be important for WinXP install) */
190 Name (_HID, EisaId ("PNP0303"))
191 Method (_STA, 0, NotSerialized)
195 Method (_CRS, 0, NotSerialized)
197 Name (TMP, ResourceTemplate () {
198 IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
199 IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
209 Name (_HID, EisaId ("PNP0F13"))
210 Method (_STA, 0, NotSerialized)
214 Method (_CRS, 0, NotSerialized)
216 Name (TMP, ResourceTemplate () {
223 /* PS/2 floppy controller */
226 Name (_HID, EisaId ("PNP0700"))
227 Method (_STA, 0, NotSerialized)
231 Method (_CRS, 0, NotSerialized)
233 Name (BUF0, ResourceTemplate () {
234 IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
235 IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
237 DMA (Compatibility, NotBusMaster, Transfer8) {2}