2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define RAMINIT_SYSINFO 1
30 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
32 unsigned int get_sbdn(unsigned bus);
34 /* Used by raminit. */
35 #define QRANK_DIMM_SUPPORT 1
37 /* Used by init_cpus and fidvid */
38 #define K8_SET_FIDVID 1
40 /* If we want to wait for core1 done before DQS training, set it to 0. */
41 #define K8_SET_FIDVID_CORE0_ONLY 1
43 #if K8_REV_F_SUPPORT == 1
44 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
47 /* #define DEBUG_SMBUS 1 */
50 #include <device/pci_def.h>
52 #include <device/pnp_def.h>
53 #include <arch/romcc_io.h>
54 #include <cpu/amd/mtrr.h>
55 #include <cpu/x86/lapic.h>
56 #include "option_table.h"
57 #include "pc80/mc146818rtc_early.c"
58 #include "pc80/serial.c"
59 #include "arch/i386/lib/console.c"
60 #include <cpu/amd/model_fxx_rev.h>
61 #include "northbridge/amd/amdk8/raminit.h"
62 #include "cpu/amd/model_fxx/apic_timer.c"
63 #include "lib/delay.c"
64 #if CONFIG_USE_INIT == 0
65 #include "lib/memcpy.c"
67 #include "cpu/x86/lapic/boot_cpu.c"
68 #include "northbridge/amd/amdk8/reset_test.c"
69 #include "northbridge/amd/amdk8/debug.c"
70 #include "northbridge/amd/amdk8/early_ht.c"
71 #include "superio/ite/it8712f/it8712f_early_serial.c"
72 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
73 #include "cpu/amd/mtrr/amd_earlymtrr.c"
74 #include "cpu/x86/bist.h"
75 #include "northbridge/amd/amdk8/setup_resource_map.c"
77 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
78 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
80 static void memreset_setup(void)
84 static void memreset(int controllers, const struct mem_controller *ctrl)
88 static inline int spd_read_byte(unsigned device, unsigned address)
90 return smbus_read_byte(device, address);
93 #define K8_4RANK_DIMM_SUPPORT 1
97 #include "northbridge/amd/amdk8/amdk8.h"
98 #include "northbridge/amd/amdk8/raminit_f.c"
99 #include "northbridge/amd/amdk8/coherent_ht.c"
100 #include "northbridge/amd/amdk8/incoherent_ht.c"
101 #include "sdram/generic_sdram.c"
102 #include "cpu/amd/dualcore/dualcore.c"
103 #include "southbridge/via/k8t890/k8t890_early_car.c"
104 #include "cpu/amd/car/copy_and_run.c"
105 #include "cpu/amd/car/post_cache_as_ram.c"
106 #include "cpu/amd/model_fxx/init_cpus.c"
110 /* this function might fail on some K8 CPUs with errata #181 */
111 static void ldtstop_sb(void)
113 print_debug("toggle LDTSTP#\r\n");
114 u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
115 reg = reg ^ (1 << 0);
116 outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
117 reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
118 print_debug("done\r\n");
122 #include "cpu/amd/model_fxx/fidvid.c"
123 #include "northbridge/amd/amdk8/resourcemap.c"
125 void activate_spd_rom(const struct mem_controller *ctrl)
129 void hard_reset(void)
131 print_info("NO HARD RESET. FIX ME!\n");
134 void soft_reset(void)
139 print_debug("soft reset \r\n");
142 tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
144 /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
145 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
148 /* daisy daisy ... */
153 unsigned int get_sbdn(unsigned bus)
157 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
158 PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
159 return (dev >> 15) & 0x1f;
167 #if USE_FALLBACK_IMAGE == 1
169 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
171 /* unsigned last_boot_normal_x = last_boot_normal(); */
173 unsigned last_boot_normal_x = 1;
176 it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
177 it8712f_kill_watchdog();
182 print_info("now booting... fallback\r\n");
184 /* Is this a CPU only reset? Or is this a secondary CPU? */
185 if ((cpu_init_detectedx) || (!boot_cpu())) {
186 if (last_boot_normal_x)
192 /* Nothing special needs to be done to find bus 0. */
193 /* Allow the HT devices to be found. */
194 enumerate_ht_chain();
196 /* Is this a deliberate reset by the BIOS? */
197 if (bios_reset_detected() && last_boot_normal_x) {
200 /* This is the primary CPU, how should I boot? */
201 else if (do_normal_boot()) {
208 /* print_info("JMP normal image\r\n"); */
210 __asm__ __volatile__("jmp __normal_image":
211 :"a" (bist), "b" (cpu_init_detectedx));
218 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
220 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
222 #if USE_FALLBACK_IMAGE == 1
223 failover_process(bist, cpu_init_detectedx);
225 real_main(bist, cpu_init_detectedx);
228 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
231 static const uint16_t spd_addr[] = {
232 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
233 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
234 #if CONFIG_MAX_PHYSICAL_CPUS > 1
235 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
236 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
239 unsigned bsp_apicid = 0;
241 struct sys_info *sysinfo =
242 (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
246 it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
247 it8712f_kill_watchdog();
252 print_info("now booting... real_main\r\n");
256 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
258 /* Halt if there was a built in self test failure. */
259 report_bist_failure(bist);
260 setup_default_resource_map();
261 setup_coherent_ht_domain();
262 wait_all_core0_started();
264 print_info("now booting... Core0 started\r\n");
266 #if CONFIG_LOGICAL_CPUS==1
267 /* It is said that we should start core1 after all core0 launched. */
269 wait_all_other_cores_started(bsp_apicid);
272 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
274 needs_reset = optimize_link_coherent_ht();
275 print_debug_hex8(needs_reset);
276 needs_reset |= optimize_link_incoherent_ht(sysinfo);
277 print_debug_hex8(needs_reset);
278 needs_reset |= k8t890_early_setup_ht();
279 print_debug_hex8(needs_reset);
281 vt8237_early_network_init(NULL);
282 vt8237_early_spi_init();
285 print_debug_hex8(needs_reset);
287 print_debug("Xht reset -\r\n");
289 print_debug("NO reset\r\n");
294 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
295 /* allow LDT STOP asserts */
296 vt8237_sb_enable_fid_vid();
299 print_debug("after enable_fid_change\r\n");
301 /* FIXME does not work yet */
302 init_fidvid_bsp(bsp_apicid);
304 /* Stop the APs so we can start them later in init. */
305 allow_all_aps_stop(bsp_apicid);
307 /* It's the time to set ctrl now. */
308 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
311 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);