2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define RAMINIT_SYSINFO 1
30 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
32 unsigned int get_sbdn(unsigned bus);
34 /* Used by raminit. */
35 #define QRANK_DIMM_SUPPORT 1
37 /* Used by init_cpus and fidvid */
38 #define K8_SET_FIDVID 1
40 /* If we want to wait for core1 done before DQS training, set it to 0. */
41 #define K8_SET_FIDVID_CORE0_ONLY 1
43 #if K8_REV_F_SUPPORT == 1
44 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
47 /* #define DEBUG_SMBUS 1 */
50 #include <device/pci_def.h>
52 #include <device/pnp_def.h>
53 #include <arch/romcc_io.h>
54 #include <cpu/amd/mtrr.h>
55 #include <cpu/x86/lapic.h>
56 #include "option_table.h"
57 #include "pc80/mc146818rtc_early.c"
58 #include "pc80/serial.c"
59 #include "arch/i386/lib/console.c"
60 #include <cpu/amd/model_fxx_rev.h>
61 #include "northbridge/amd/amdk8/raminit.h"
62 #include "cpu/amd/model_fxx/apic_timer.c"
63 #include "lib/delay.c"
64 #if CONFIG_USE_INIT == 0
65 #include "lib/memcpy.c"
67 #include "cpu/x86/lapic/boot_cpu.c"
68 #include "northbridge/amd/amdk8/reset_test.c"
69 #include "northbridge/amd/amdk8/debug.c"
70 #include "northbridge/amd/amdk8/early_ht.c"
71 #include "superio/ite/it8712f/it8712f_early_serial.c"
72 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
73 #include "cpu/amd/mtrr/amd_earlymtrr.c"
74 #include "cpu/x86/bist.h"
75 #include "northbridge/amd/amdk8/setup_resource_map.c"
77 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
78 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
80 static void memreset_setup(void)
84 static void memreset(int controllers, const struct mem_controller *ctrl)
88 static inline int spd_read_byte(unsigned device, unsigned address)
90 return smbus_read_byte(device, address);
93 #define K8_4RANK_DIMM_SUPPORT 1
95 #include "northbridge/amd/amdk8/amdk8.h"
96 #include "northbridge/amd/amdk8/raminit_f.c"
97 #include "northbridge/amd/amdk8/coherent_ht.c"
98 #include "northbridge/amd/amdk8/incoherent_ht.c"
99 #include "sdram/generic_sdram.c"
100 #include "cpu/amd/dualcore/dualcore.c"
101 #include "southbridge/via/k8t890/k8t890_early_car.c"
102 #include "cpu/amd/car/copy_and_run.c"
103 #include "cpu/amd/car/post_cache_as_ram.c"
104 #include "cpu/amd/model_fxx/init_cpus.c"
105 #include "cpu/amd/model_fxx/fidvid.c"
106 #include "northbridge/amd/amdk8/resourcemap.c"
108 void activate_spd_rom(const struct mem_controller *ctrl)
112 void hard_reset(void)
114 print_info("NO HARD RESET. FIX ME!\n");
117 void soft_reset(void)
122 print_debug("soft reset \r\n");
125 tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
127 /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
128 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
131 /* daisy daisy ... */
136 unsigned int get_sbdn(unsigned bus)
140 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
141 PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
142 return (dev >> 15) & 0x1f;
150 #if USE_FALLBACK_IMAGE == 1
152 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
154 /* unsigned last_boot_normal_x = last_boot_normal(); */
156 unsigned last_boot_normal_x = 1;
159 it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
160 it8712f_kill_watchdog();
165 print_info("now booting... fallback\r\n");
167 /* Is this a CPU only reset? Or is this a secondary CPU? */
168 if ((cpu_init_detectedx) || (!boot_cpu())) {
169 if (last_boot_normal_x)
175 /* Nothing special needs to be done to find bus 0. */
176 /* Allow the HT devices to be found. */
177 enumerate_ht_chain();
179 /* Is this a deliberate reset by the BIOS? */
180 if (bios_reset_detected() && last_boot_normal_x) {
183 /* This is the primary CPU, how should I boot? */
184 else if (do_normal_boot()) {
191 /* print_info("JMP normal image\r\n"); */
193 __asm__ __volatile__("jmp __normal_image":
194 :"a" (bist), "b" (cpu_init_detectedx));
201 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
203 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
205 #if USE_FALLBACK_IMAGE == 1
206 failover_process(bist, cpu_init_detectedx);
208 real_main(bist, cpu_init_detectedx);
211 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
214 static const uint16_t spd_addr[] = {
215 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
216 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
217 #if CONFIG_MAX_PHYSICAL_CPUS > 1
218 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
219 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
222 unsigned bsp_apicid = 0;
224 struct sys_info *sysinfo =
225 (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
229 it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
230 it8712f_kill_watchdog();
235 print_info("now booting... real_main\r\n");
239 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
241 /* Halt if there was a built in self test failure. */
242 report_bist_failure(bist);
243 setup_default_resource_map();
244 setup_coherent_ht_domain();
245 wait_all_core0_started();
247 print_info("now booting... Core0 started\r\n");
249 #if CONFIG_LOGICAL_CPUS==1
250 /* It is said that we should start core1 after all core0 launched. */
252 wait_all_other_cores_started(bsp_apicid);
255 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
257 needs_reset = optimize_link_coherent_ht();
258 print_debug_hex8(needs_reset);
259 needs_reset |= optimize_link_incoherent_ht(sysinfo);
260 print_debug_hex8(needs_reset);
261 needs_reset |= k8t890_early_setup_ht();
262 print_debug_hex8(needs_reset);
264 vt8237_early_network_init(NULL);
265 vt8237_early_spi_init();
268 print_debug_hex8(needs_reset);
270 print_debug("Xht reset -\r\n");
272 print_debug("NO reset\r\n");
277 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
278 /* allow LDT STOP asserts */
279 vt8237_sb_enable_fid_vid();
282 print_debug("after enable_fid_change\r\n");
284 /* FIXME does not work yet */
285 init_fidvid_bsp(bsp_apicid);
287 /* Stop the APs so we can start them later in init. */
288 allow_all_aps_stop(bsp_apicid);
290 /* It's the time to set ctrl now. */
291 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
294 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);