src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2006 MSI
   7  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
   8  * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define ASSEMBLY 1
  26 #define __ROMCC__
  27
  28 #define RAMINIT_SYSINFO 1
  29
  30 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
  31
  32 unsigned int get_sbdn(unsigned bus);
  33
  34 /* Used by raminit. */
  35 #define QRANK_DIMM_SUPPORT 1
  36
  37 /* Used by init_cpus and fidvid */
  38 #define K8_SET_FIDVID 1
  39
  40 /* If we want to wait for core1 done before DQS training, set it to 0. */
  41 #define K8_SET_FIDVID_CORE0_ONLY 1
  42
  43 #if K8_REV_F_SUPPORT == 1
  44 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  45 #endif
  46
  47 /* #define DEBUG_SMBUS 1 */
  48
  49 #include <stdint.h>
  50 #include <device/pci_def.h>
  51 #include <arch/io.h>
  52 #include <device/pnp_def.h>
  53 #include <arch/romcc_io.h>
  54 #include <cpu/amd/mtrr.h>
  55 #include <cpu/x86/lapic.h>
  56 #include "option_table.h"
  57 #include "pc80/mc146818rtc_early.c"
  58 #include "pc80/serial.c"
  59 #include "arch/i386/lib/console.c"
  60 #include <cpu/amd/model_fxx_rev.h>
  61 #include "northbridge/amd/amdk8/raminit.h"
  62 #include "cpu/amd/model_fxx/apic_timer.c"
  63 #include "lib/delay.c"
  64 #if CONFIG_USE_INIT == 0
  65 #include "lib/memcpy.c"
  66 #endif
  67 #include "cpu/x86/lapic/boot_cpu.c"
  68 #include "northbridge/amd/amdk8/reset_test.c"
  69 #include "northbridge/amd/amdk8/debug.c"
  70 #include "northbridge/amd/amdk8/early_ht.c"
  71 #include "superio/ite/it8712f/it8712f_early_serial.c"
  72 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
  73 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  74 #include "cpu/x86/bist.h"
  75 #include "northbridge/amd/amdk8/setup_resource_map.c"
  76
  77 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
  78 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
  79
  80 static void memreset_setup(void)
  81 {
  82 }
  83
  84 static void memreset(int controllers, const struct mem_controller *ctrl)
  85 {
  86 }
  87
  88 static inline int spd_read_byte(unsigned device, unsigned address)
  89 {
  90         return smbus_read_byte(device, address);
  91 }
  92
  93 #define K8_4RANK_DIMM_SUPPORT 1
  94
  95 #include "northbridge/amd/amdk8/amdk8.h"
  96 #include "northbridge/amd/amdk8/raminit_f.c"
  97 #include "northbridge/amd/amdk8/coherent_ht.c"
  98 #include "northbridge/amd/amdk8/incoherent_ht.c"
  99 #include "sdram/generic_sdram.c"
 100 #include "cpu/amd/dualcore/dualcore.c"
 101 #include "southbridge/via/k8t890/k8t890_early_car.c"
 102 #include "cpu/amd/car/copy_and_run.c"
 103 #include "cpu/amd/car/post_cache_as_ram.c"
 104 #include "cpu/amd/model_fxx/init_cpus.c"
 105 #include "cpu/amd/model_fxx/fidvid.c"
 106 #include "northbridge/amd/amdk8/resourcemap.c"
 107
 108 void activate_spd_rom(const struct mem_controller *ctrl)
 109 {
 110 }
 111
 112 void hard_reset(void)
 113 {
 114         print_info("NO HARD RESET. FIX ME!\n");
 115 }
 116
 117 void soft_reset(void)
 118 {
 119         uint8_t tmp;
 120
 121         set_bios_reset();
 122         print_debug("soft reset \r\n");
 123
 124         /* PCI reset */
 125         tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
 126         tmp |= 0x01;
 127         /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
 128         pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 129
 130         while (1) {
 131                 /* daisy daisy ... */
 132                 hlt();
 133         }
 134 }
 135
 136 unsigned int get_sbdn(unsigned bus)
 137 {
 138         device_t dev;
 139
 140         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 141                                         PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
 142         return (dev >> 15) & 0x1f;
 143 }
 144
 145 void sio_init(void)
 146 {
 147
 148 }
 149
 150 #if USE_FALLBACK_IMAGE == 1
 151
 152 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 153 {
 154         /* unsigned last_boot_normal_x = last_boot_normal(); */
 155         /* FIXME */
 156         unsigned last_boot_normal_x = 1;
 157
 158         sio_init();
 159         it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
 160         uart_init();
 161         console_init();
 162         enable_rom_decode();
 163
 164         print_info("now booting... fallback\r\n");
 165
 166         /* Is this a CPU only reset? Or is this a secondary CPU? */
 167         if ((cpu_init_detectedx) || (!boot_cpu())) {
 168                 if (last_boot_normal_x)
 169                         goto normal_image;
 170                 else
 171                         goto fallback_image;
 172         }
 173
 174         /* Nothing special needs to be done to find bus 0. */
 175         /* Allow the HT devices to be found. */
 176         enumerate_ht_chain();
 177
 178         /* Is this a deliberate reset by the BIOS? */
 179         if (bios_reset_detected() && last_boot_normal_x) {
 180                 goto normal_image;
 181         }
 182         /* This is the primary CPU, how should I boot? */
 183         else if (do_normal_boot()) {
 184                 goto normal_image;
 185         } else {
 186                 goto fallback_image;
 187         }
 188
 189 normal_image:
 190         /* print_info("JMP normal image\r\n"); */
 191
 192         __asm__ __volatile__("jmp __normal_image":
 193                              :"a" (bist), "b" (cpu_init_detectedx));
 194
 195 fallback_image:
 196         ;
 197 }
 198 #endif
 199
 200 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 201
 202 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 203 {
 204 #if USE_FALLBACK_IMAGE == 1
 205         failover_process(bist, cpu_init_detectedx);
 206 #endif
 207         real_main(bist, cpu_init_detectedx);
 208 }
 209
 210 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 211 {
 212         msr_t msr;
 213         static const uint16_t spd_addr[] = {
 214                 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
 215                 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
 216 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 217                 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
 218                 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
 219 #endif
 220         };
 221         unsigned bsp_apicid = 0;
 222         int needs_reset = 0;
 223         struct sys_info *sysinfo =
 224             (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 225         char *p;
 226
 227         sio_init();
 228         it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
 229         uart_init();
 230         console_init();
 231         enable_rom_decode();
 232
 233         print_info("now booting... real_main\r\n");
 234
 235
 236         if (bist == 0)
 237                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 238
 239         /* Halt if there was a built in self test failure. */
 240         report_bist_failure(bist);
 241         setup_default_resource_map();
 242         setup_coherent_ht_domain();
 243         wait_all_core0_started();
 244
 245         print_info("now booting... Core0 started\r\n");
 246
 247 #if CONFIG_LOGICAL_CPUS==1
 248         /* It is said that we should start core1 after all core0 launched. */
 249         start_other_cores();
 250         wait_all_other_cores_started(bsp_apicid);
 251 #endif
 252         init_timer();
 253         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 254
 255         needs_reset = optimize_link_coherent_ht();
 256         print_debug_hex8(needs_reset);
 257         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 258         print_debug_hex8(needs_reset);
 259         needs_reset |= k8t890_early_setup_ht();
 260         print_debug_hex8(needs_reset);
 261
 262         vt8237_early_network_init(NULL);
 263         vt8237_early_spi_init();
 264
 265         if (needs_reset) {
 266                 print_debug_hex8(needs_reset);
 267
 268                 print_debug("Xht reset -\r\n");
 269                 soft_reset();
 270                 print_debug("NO reset\r\n");
 271
 272         }
 273
 274
 275         /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
 276         /* allow LDT STOP asserts */
 277         vt8237_sb_enable_fid_vid();
 278
 279         enable_fid_change();
 280         print_debug("after enable_fid_change\r\n");
 281
 282         /* FIXME does not work yet */
 283 //      init_fidvid_bsp(bsp_apicid);
 284
 285         /* Stop the APs so we can start them later in init. */
 286         allow_all_aps_stop(bsp_apicid);
 287
 288         /* It's the time to set ctrl now. */
 289         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 290         enable_smbus();
 291         memreset_setup();
 292         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 293         post_cache_as_ram();
 294 }