2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 ## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, write to the Free Software
20 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 default ROM_SECTION_SIZE = FALLBACK_SIZE
25 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
27 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
28 default ROM_SECTION_OFFSET = 0
31 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
32 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
33 default CONFIG_ROM_PAYLOAD = 1
34 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
36 ##WARNING enable caching of whole ROM during CAR
37 default XIP_ROM_SIZE = ROM_SIZE
38 default XIP_ROM_BASE = 0xffffffff + 1 - XIP_ROM_SIZE
47 depends "$(MAINBOARD)/dsdt.asl"
48 action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
49 action "mv dsdt.hex dsdt.c"
53 if HAVE_MP_TABLE object mptable.o end
54 if HAVE_PIRQ_TABLE object irq_tables.o end
59 makerule ./cache_as_ram_auto.o
60 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
61 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
64 makerule ./cache_as_ram_auto.inc
65 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
66 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
67 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
68 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
74 mainboardinit cpu/x86/16bit/entry16.inc
75 ldscript /cpu/x86/16bit/entry16.lds
76 mainboardinit southbridge/via/k8t890/romstrap.inc
77 ldscript /southbridge/via/k8t890/romstrap.lds
80 mainboardinit cpu/x86/32bit/entry32.inc
84 ldscript /cpu/x86/32bit/entry32.lds
87 ldscript /cpu/amd/car/cache_as_ram.lds
92 mainboardinit cpu/x86/16bit/reset16.inc
93 ldscript /cpu/x86/16bit/reset16.lds
95 mainboardinit cpu/x86/32bit/reset32.inc
96 ldscript /cpu/x86/32bit/reset32.lds
100 mainboardinit cpu/amd/car/cache_as_ram.inc
103 if USE_FALLBACK_IMAGE
105 ldscript /arch/i386/lib/failover.lds
111 initobject cache_as_ram_auto.o
113 mainboardinit ./cache_as_ram_auto.inc
121 chip northbridge/amd/amdk8/root_complex # Root complex
122 device apic_cluster 0 on # APIC cluster
123 chip cpu/amd/socket_AM2 # CPU
124 device apic 0 on end # APIC
127 device pci_domain 0 on # PCI domain
128 chip northbridge/amd/amdk8 # mc0
129 device pci 18.0 on # Northbridge
130 # Devices on link 0, link 0 == LDT 0
131 chip southbridge/via/vt8237r # Southbridge
132 register "ide0_enable" = "1" # Enable IDE channel 0
133 register "ide1_enable" = "1" # Enable IDE channel 1
134 register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
135 register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
136 register "fn_ctrl_lo" = "0xc0" # Enable SB functions
137 register "fn_ctrl_hi" = "0x1d" # Enable SB functions
138 device pci 0.0 on end # HT
139 device pci f.1 on end # IDE
140 device pci 11.0 on # LPC
141 chip drivers/generic/generic # DIMM 0-0-0
144 chip drivers/generic/generic # DIMM 0-0-1
147 chip drivers/generic/generic # DIMM 0-1-0
150 chip drivers/generic/generic # DIMM 0-1-1
153 chip superio/ite/it8712f # Super I/O
154 device pnp 2e.0 on # Floppy
159 device pnp 2e.1 on # Com1
163 device pnp 2e.2 off # Com2
167 device pnp 2e.3 on # Parallel port
171 device pnp 2e.4 on # Environment controller
176 device pnp 2e.5 off end # PS/2 keyboard
177 device pnp 2e.6 off end # PS/2 mouse
178 device pnp 2e.7 off end # GPIO config
179 device pnp 2e.8 off end # Midi port
180 device pnp 2e.9 off end # Game port
181 device pnp 2e.a off end # IR
184 device pci 12.0 on end # VIA LAN
185 device pci 13.0 on end # br
186 device pci 13.1 on end # br2 need to have it here to discover it
188 chip southbridge/via/k8t890 # "Southbridge" K8M890
191 device pci 18.1 on end
192 device pci 18.2 on end
193 device pci 18.3 on end