2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 ## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, write to the Free Software
20 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 include /config/nofailovercalculation128.lb
31 depends "$(MAINBOARD)/dsdt.asl"
32 action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
33 action "mv dsdt.hex dsdt.c"
39 makerule ./cache_as_ram_auto.o
40 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
41 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
44 makerule ./cache_as_ram_auto.inc
45 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
46 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
47 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
48 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
53 mainboardinit cpu/x86/16bit/entry16.inc
54 ldscript /cpu/x86/16bit/entry16.lds
55 mainboardinit southbridge/via/k8t890/romstrap.inc
56 ldscript /southbridge/via/k8t890/romstrap.lds
59 mainboardinit cpu/x86/32bit/entry32.inc
62 ldscript /cpu/x86/32bit/entry32.lds
65 ldscript /cpu/amd/car/cache_as_ram.lds
69 mainboardinit cpu/x86/16bit/reset16.inc
70 ldscript /cpu/x86/16bit/reset16.lds
72 mainboardinit cpu/x86/32bit/reset32.inc
73 ldscript /cpu/x86/32bit/reset32.lds
76 mainboardinit cpu/amd/car/cache_as_ram.inc
79 ldscript /arch/i386/lib/failover.lds
83 initobject cache_as_ram_auto.o
85 mainboardinit ./cache_as_ram_auto.inc
90 chip northbridge/amd/amdk8/root_complex # Root complex
91 device apic_cluster 0 on # APIC cluster
92 chip cpu/amd/socket_AM2 # CPU
93 device apic 0 on end # APIC
96 device pci_domain 0 on # PCI domain
97 chip northbridge/amd/amdk8 # mc0
98 device pci 18.0 on # Northbridge
99 # Devices on link 0, link 0 == LDT 0
100 chip southbridge/via/vt8237r # Southbridge
101 register "ide0_enable" = "1" # Enable IDE channel 0
102 register "ide1_enable" = "1" # Enable IDE channel 1
103 register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
104 register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
105 register "fn_ctrl_lo" = "0xc0" # Enable SB functions
106 register "fn_ctrl_hi" = "0x1d" # Enable SB functions
107 device pci 0.0 on end # HT
108 device pci f.1 on end # IDE
109 device pci 11.0 on # LPC
110 chip drivers/generic/generic # DIMM 0-0-0
113 chip drivers/generic/generic # DIMM 0-0-1
116 chip drivers/generic/generic # DIMM 0-1-0
119 chip drivers/generic/generic # DIMM 0-1-1
122 chip superio/ite/it8712f # Super I/O
123 device pnp 2e.0 on # Floppy
128 device pnp 2e.1 on # Com1
132 device pnp 2e.2 off # Com2
136 device pnp 2e.3 on # Parallel port
140 device pnp 2e.4 on # Environment controller
145 device pnp 2e.5 off end # PS/2 keyboard
146 device pnp 2e.6 off end # PS/2 mouse
147 device pnp 2e.7 off end # GPIO config
148 device pnp 2e.8 off end # Midi port
149 device pnp 2e.9 off end # Game port
150 device pnp 2e.a off end # IR
153 device pci 12.0 on end # VIA LAN
154 device pci 13.0 on end # br
155 device pci 13.1 on end # br2 need to have it here to discover it
157 chip southbridge/via/k8t890 # "Southbridge" K8M890
160 device pci 18.1 on end
161 device pci 18.2 on end
162 device pci 18.3 on end