2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
26 #include <cpu/amd/amdk8_sysconf.h>
28 #define PCI_INT(bus, dev, fn, pin) \
29 smp_write_intsrc(mc, mp_INT, \
30 MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, \
31 bus_mcp55[bus], (((dev) << 2) | (fn)), apicid_mcp55, (pin))
33 extern unsigned char bus_mcp55[8];
34 extern unsigned apicid_mcp55;
36 static void *smp_write_config_table(void *v)
38 struct mp_config_table *mc;
44 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 mptable_init(mc, LOCAL_APIC_ADDR);
48 smp_write_processors(mc);
53 mptable_write_buses(mc, NULL, &bus_isa);
55 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
57 res = find_resource(dev, PCI_BASE_ADDRESS_1);
59 smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
61 pci_write_config32(dev, 0x7c, 0x00000000);
62 pci_write_config32(dev, 0x80, 0x11002009);
63 pci_write_config32(dev, 0x84, 0x2000dd08);
66 mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
69 PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */
70 PCI_INT(0, sbdn + 2, 0, 20); /* USB 1.1 */
71 PCI_INT(0, sbdn + 2, 1, 22); /* USB 2.0 */
72 PCI_INT(0, sbdn + 4, 0, 14); /* IDE */
73 PCI_INT(0, sbdn + 5, 0, 23); /* SATA 0 */
74 PCI_INT(0, sbdn + 5, 1, 23); /* SATA 1 */
75 PCI_INT(0, sbdn + 5, 2, 22); /* SATA 2 */
76 PCI_INT(0, sbdn + 6, 1, 21); /* HD audio */
77 PCI_INT(0, sbdn + 8, 0, 24); /* NIC */
79 /* PCI-E slots (two x1, one x4, one x16) */
80 for (j = 7; j >= 2; j--) {
83 for (i = 0; i < 4; i++)
84 PCI_INT(j, 0, i, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
87 /* PCI slots (three on this board) */
88 for (j = 0; j < 3; j++) {
89 for (i = 0; i < 4; i++)
90 PCI_INT(1, 0x06 + j, i, 0x10 + (2 + i + j) % 4);
93 /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
94 mptable_lintsrc(mc, bus_isa);
96 /* Compute the checksums. */
97 return mptable_finalize(mc);
100 unsigned long write_smp_table(unsigned long addr)
103 v = smp_write_floating_table(addr, 0);
104 return (unsigned long)smp_write_config_table(v);