2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define RAMINIT_SYSINFO 1
30 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
32 unsigned int get_sbdn(unsigned bus);
34 /* Used by raminit. */
35 #define QRANK_DIMM_SUPPORT 1
37 /* Used by init_cpus and fidvid */
38 #define K8_SET_FIDVID 1
40 /* If we want to wait for core1 done before DQS training, set it to 0. */
41 #define K8_SET_FIDVID_CORE0_ONLY 1
45 #include <device/pci_def.h>
47 #include <device/pnp_def.h>
48 #include <arch/romcc_io.h>
49 #include <cpu/x86/lapic.h>
50 #include "option_table.h"
51 #include "pc80/mc146818rtc_early.c"
52 #include "pc80/serial.c"
53 #include "arch/i386/lib/console.c"
54 #include <cpu/amd/model_fxx_rev.h>
55 #include "northbridge/amd/amdk8/raminit.h"
56 #include "cpu/amd/model_fxx/apic_timer.c"
57 #include "lib/delay.c"
58 #include "cpu/x86/lapic/boot_cpu.c"
59 #include "northbridge/amd/amdk8/reset_test.c"
60 #include "northbridge/amd/amdk8/early_ht.c"
61 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
62 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
63 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
64 #include "cpu/amd/mtrr/amd_earlymtrr.c"
65 #include "cpu/x86/bist.h"
66 #include "northbridge/amd/amdk8/setup_resource_map.c"
68 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
69 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
70 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
71 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
73 static void memreset_setup(void)
77 static void memreset(int controllers, const struct mem_controller *ctrl)
81 static inline int spd_read_byte(unsigned device, unsigned address)
83 return smbus_read_byte(device, address);
86 void activate_spd_rom(const struct mem_controller *ctrl)
95 print_debug("soft reset \r\n");
98 tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
100 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
103 /* daisy daisy ... */
108 #define K8_4RANK_DIMM_SUPPORT 1
110 #include "northbridge/amd/amdk8/amdk8.h"
111 #include "northbridge/amd/amdk8/raminit.c"
112 #include "northbridge/amd/amdk8/coherent_ht.c"
113 #include "northbridge/amd/amdk8/incoherent_ht.c"
114 #include "lib/generic_sdram.c"
115 #include "cpu/amd/dualcore/dualcore.c"
116 #include "southbridge/via/k8t890/k8t890_early_car.c"
117 #include "cpu/amd/car/copy_and_run.c"
118 #include "cpu/amd/car/post_cache_as_ram.c"
119 #include "cpu/amd/model_fxx/init_cpus.c"
120 #include "cpu/amd/model_fxx/fidvid.c"
121 #include "northbridge/amd/amdk8/resourcemap.c"
123 void hard_reset(void)
125 print_info("NO HARD RESET. FIX ME!\n");
128 unsigned int get_sbdn(unsigned bus)
132 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
133 PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
134 return (dev >> 15) & 0x1f;
141 pnp_enter_ext_func_mode(SERIAL_DEV);
142 /* We have 24MHz input. */
143 reg = pnp_read_config(SERIAL_DEV, 0x24);
144 pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
145 /* We have GPIO for KB/MS pin. */
146 reg = pnp_read_config(SERIAL_DEV, 0x2a);
147 pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
148 /* We have all RESTOUT and even some reserved bits, too. */
149 reg = pnp_read_config(SERIAL_DEV, 0x2c);
150 pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
151 pnp_exit_ext_func_mode(SERIAL_DEV);
153 pnp_enter_ext_func_mode(ACPI_DEV);
154 pnp_set_logical_device(ACPI_DEV);
156 * Set the delay rising time from PWROK_LP to PWROK_ST to
157 * 300 - 600ms, and 0 to vice versa.
159 reg = pnp_read_config(ACPI_DEV, 0xe6);
160 pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
161 /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
162 reg = pnp_read_config(ACPI_DEV, 0xe4);
163 pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
164 pnp_exit_ext_func_mode(ACPI_DEV);
166 pnp_enter_ext_func_mode(GPIO_DEV);
167 pnp_set_logical_device(GPIO_DEV);
168 /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
169 pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
170 pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
171 pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
172 pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
173 pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
174 pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
175 pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
176 pnp_exit_ext_func_mode(GPIO_DEV);
179 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
181 static const uint16_t spd_addr[] = {
182 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
183 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
184 #if CONFIG_MAX_PHYSICAL_CPUS > 1
185 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
186 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
189 unsigned bsp_apicid = 0;
191 struct sys_info *sysinfo =
192 (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
196 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
201 print_info("now booting... fallback\r\n");
203 /* Is this a CPU only reset? Or is this a secondary CPU? */
204 if (!cpu_init_detectedx && boot_cpu()) {
205 /* Nothing special needs to be done to find bus 0. */
206 /* Allow the HT devices to be found. */
207 enumerate_ht_chain();
211 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
216 print_info("now booting... real_main\r\n");
219 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
221 /* Halt if there was a built in self test failure. */
222 report_bist_failure(bist);
224 setup_default_resource_map();
225 setup_coherent_ht_domain();
226 wait_all_core0_started();
228 print_info("now booting... Core0 started\r\n");
230 #if CONFIG_LOGICAL_CPUS==1
231 /* It is said that we should start core1 after all core0 launched. */
233 wait_all_other_cores_started(bsp_apicid);
236 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
238 needs_reset = optimize_link_coherent_ht();
239 needs_reset |= optimize_link_incoherent_ht(sysinfo);
240 needs_reset |= k8t890_early_setup_ht();
243 print_debug("ht reset -\r\n");
247 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
249 init_fidvid_bsp(bsp_apicid);
251 /* Stop the APs so we can start them later in init. */
252 allow_all_aps_stop(bsp_apicid);
254 /* It's the time to set ctrl now. */
255 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
259 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);