2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 ## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, write to the Free Software
20 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 default ROM_SECTION_SIZE = FALLBACK_SIZE
25 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
27 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
28 default ROM_SECTION_OFFSET = 0
31 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
32 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
33 default CONFIG_ROM_PAYLOAD = 1
34 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
35 default XIP_ROM_SIZE = 65536
36 default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
45 depends "$(MAINBOARD)/dsdt.asl"
46 action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
47 action "mv dsdt.hex dsdt.c"
51 if HAVE_MP_TABLE object mptable.o end
52 if HAVE_PIRQ_TABLE object irq_tables.o end
57 makerule ./cache_as_ram_auto.o
58 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
62 makerule ./cache_as_ram_auto.inc
63 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
64 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
65 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
66 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
72 mainboardinit cpu/x86/16bit/entry16.inc
73 ldscript /cpu/x86/16bit/entry16.lds
74 mainboardinit southbridge/via/k8t890/romstrap.inc
75 ldscript /southbridge/via/k8t890/romstrap.lds
78 mainboardinit cpu/x86/32bit/entry32.inc
82 ldscript /cpu/x86/32bit/entry32.lds
85 ldscript /cpu/amd/car/cache_as_ram.lds
90 mainboardinit cpu/x86/16bit/reset16.inc
91 ldscript /cpu/x86/16bit/reset16.lds
93 mainboardinit cpu/x86/32bit/reset32.inc
94 ldscript /cpu/x86/32bit/reset32.lds
98 mainboardinit cpu/amd/car/cache_as_ram.inc
101 if USE_FALLBACK_IMAGE
103 ldscript /arch/i386/lib/failover.lds
109 initobject cache_as_ram_auto.o
111 mainboardinit ./cache_as_ram_auto.inc
119 chip northbridge/amd/amdk8/root_complex # Root complex
120 device apic_cluster 0 on # APIC cluster
121 chip cpu/amd/socket_939 # CPU
122 device apic 0 on end # APIC
125 device pci_domain 0 on # PCI domain
126 chip northbridge/amd/amdk8 # mc0
127 device pci 18.0 on # Northbridge
128 # Devices on link 0, link 0 == LDT 0
129 chip southbridge/via/vt8237r # Southbridge
130 register "ide0_enable" = "1" # Enable IDE channel 0
131 register "ide1_enable" = "1" # Enable IDE channel 1
132 register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
133 register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
134 register "fn_ctrl_lo" = "0" # Enable SB functions
135 register "fn_ctrl_hi" = "0xad" # Enable SB functions
136 device pci 0.0 on end # HT
137 device pci f.1 on end # IDE
138 device pci 11.0 on # LPC
139 chip drivers/generic/generic # DIMM 0-0-0
142 chip drivers/generic/generic # DIMM 0-0-1
145 chip drivers/generic/generic # DIMM 0-1-0
148 chip drivers/generic/generic # DIMM 0-1-1
151 chip superio/winbond/w83627ehg # Super I/O
152 device pnp 2e.0 on # Floppy
157 device pnp 2e.1 on # Parallel port
162 device pnp 2e.2 on # Com1
166 device pnp 2e.3 off # Com2 (N/A on this board)
170 device pnp 2e.5 off # PS/2 keyboard (off)
172 device pnp 2e.106 off # Serial flash
175 device pnp 2e.007 off # GPIO 1
177 device pnp 2e.107 on # Game port
180 device pnp 2e.207 on # MIDI
184 device pnp 2e.307 off # GPIO 6
186 device pnp 2e.8 off # WDTO_PLED
188 device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup
190 device pnp 2e.109 off # GPIO 3
192 device pnp 2e.209 off # GPIO 4
194 device pnp 2e.309 on # GPIO5
196 device pnp 2e.a off # ACPI
198 device pnp 2e.b on # Hardware monitor
204 device pci 12.0 off end # VIA LAN (off, other chip used)
206 chip southbridge/via/k8t890 # "Southbridge" K8T890
209 device pci 18.1 on end
210 device pci 18.2 on end
211 device pci 18.3 on end