2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <arch/smp/mpspec.h>
26 #include <device/pci.h>
29 #include <cpu/amd/amdk8_sysconf.h>
31 extern unsigned char bus_ck804[6];
32 extern unsigned apicid_ck804;
34 static void *smp_write_config_table(void *v)
36 struct mp_config_table *mc;
40 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
42 mptable_init(mc, LAPIC_ADDR);
44 smp_write_processors(mc);
49 mptable_write_buses(mc, NULL, &bus_isa);
51 /* I/O APICs: APIC ID Version State Address */
57 dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
59 res = find_resource(dev, PCI_BASE_ADDRESS_1);
61 smp_write_ioapic(mc, apicid_ck804, 0x11,
65 /* Initialize interrupt mapping. */
67 pci_write_config32(dev, 0x7c, dword);
70 pci_write_config32(dev, 0x80, dword);
73 pci_write_config32(dev, 0x84, dword);
78 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
80 // Onboard ck804 smbus
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
82 bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
85 // Onboard ck804 USB 1.1
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
87 bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
90 // Onboard ck804 USB 2
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
92 bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
95 // Onboard ck804 SATA 0
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
97 bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
100 // Onboard ck804 SATA 1
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
102 bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
107 bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
110 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
111 mptable_lintsrc(mc, bus_ck804[0]);
113 /* There is no extension information... */
115 /* Compute the checksums. */
116 return mptable_finalize(mc);
119 unsigned long write_smp_table(unsigned long addr)
121 void *v = smp_write_floating_table(addr, 0);
122 return (unsigned long)smp_write_config_table(v);