2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
30 #if CONFIG_LOGICAL_CPUS == 1
31 #include <cpu/amd/dualcore.h>
33 #include <cpu/amd/amdk8_sysconf.h>
37 * Global variables for MB layouts and these will be shared by irqtable,
38 * mptable and acpi_tables.
40 /* busnum is default */
41 unsigned char bus_isa;
42 unsigned char bus_ck804[6];
43 unsigned apicid_ck804;
46 * Here you only need to set value in pci1234 for HT-IO that could be installed
47 * or not. You may need to preset pci1234 for HT-IO board, please refer to
48 * src/northbridge/amd/amdk8/get_sblk_pci1234.c for details.
50 unsigned pci1234x[] = {
51 0x0000ff0, /* No HTIO for A8N-E */
55 * HT Chain device num, actually it is unit id base of every ht device in
56 * chain, assume every chain only have 4 ht device at most.
59 0x20202020, /* A8N-E has only one ht-chain */
62 unsigned bus_type[256];
64 extern void get_sblk_pci1234(void);
66 static unsigned get_bus_conf_done = 0;
68 void get_bus_conf(void)
70 unsigned apicid_base, sbdn;
74 if (get_bus_conf_done == 1)
75 return; /* Do it only once. */
77 get_bus_conf_done = 1;
79 /* FIXME: Is this really needed twice? */
80 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
81 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
82 for (i = 0; i < sysconf.hc_possible_num; i++) {
83 sysconf.pci1234[i] = pci1234x[i];
84 sysconf.hcdn[i] = hcdnx[i];
89 sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
92 for (i = 0; i < 6; i++)
94 for (i = 0; i < 256; i++)
97 bus_type[0] = 1; /* PCI */
99 bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
101 bus_type[bus_ck804[0]] = 1;
104 dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
106 bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
107 bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
111 (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
117 for (i = 2; i < 6; i++) {
118 dev = dev_find_slot(bus_ck804[0],
119 PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
121 bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
122 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
124 for (j = bus_ck804[i]; j < bus_isa; j++)
127 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
128 bus_ck804[0], sbdn + 0x0b + i - 2);
129 bus_isa = bus_ck804[i - 1] + 1;
133 #if CONFIG_LOGICAL_CPUS==1
134 apicid_base = get_apicid_base(3);
136 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
138 apicid_ck804 = apicid_base + 0;