2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 /* Used by it8712f_enable_serial(). */
28 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
30 /* Used by raminit. */
31 #define QRANK_DIMM_SUPPORT 1
33 /* Turn this on for SMBus debugging output. */
36 #if CONFIG_LOGICAL_CPUS == 1
37 #define SET_NB_CFG_54 1
41 #include <device/pci_def.h>
43 #include <device/pnp_def.h>
44 #include <arch/romcc_io.h>
45 #include <cpu/x86/lapic.h>
46 #include "option_table.h"
47 #include "pc80/mc146818rtc_early.c"
48 #include "cpu/x86/lapic/boot_cpu.c"
49 #include "northbridge/amd/amdk8/reset_test.c"
50 #include "superio/ite/it8712f/it8712f_early_serial.c"
52 #if USE_FAILOVER_IMAGE == 0
54 /* Used by ck894_early_setup(). */
57 #if CONFIG_USE_INIT == 0
58 #include "lib/memcpy.c"
61 #include <cpu/amd/model_fxx_rev.h>
62 #include "pc80/serial.c"
63 #include "arch/i386/lib/console.c"
64 #include "ram/ramtest.c"
65 #include "northbridge/amd/amdk8/incoherent_ht.c"
66 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
67 #include "northbridge/amd/amdk8/raminit.h"
68 #include "cpu/amd/model_fxx/apic_timer.c"
69 #include "lib/delay.c"
70 #include "northbridge/amd/amdk8/debug.c"
71 #include "cpu/amd/mtrr/amd_earlymtrr.c"
72 #include "cpu/x86/bist.h"
73 #include "northbridge/amd/amdk8/setup_resource_map.c"
74 #include "northbridge/amd/amdk8/coherent_ht.c"
75 #include "cpu/amd/dualcore/dualcore.c"
77 static void memreset_setup(void)
79 /* FIXME: Nothing to do? */
82 static void memreset(int controllers, const struct mem_controller *ctrl)
84 /* FIXME: Nothing to do? */
87 static inline void activate_spd_rom(const struct mem_controller *ctrl)
89 /* FIXME: Nothing to do? */
92 static inline int spd_read_byte(unsigned device, unsigned address)
94 return smbus_read_byte(device, address);
97 #include "northbridge/amd/amdk8/raminit.c"
98 #include "sdram/generic_sdram.c"
99 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
100 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
101 #include "cpu/amd/car/copy_and_run.c"
102 #include "cpu/amd/car/post_cache_as_ram.c"
103 #include "cpu/amd/model_fxx/init_cpus.c"
105 #endif /* USE_FAILOVER_IMAGE */
107 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \
108 || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
110 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
111 #include "northbridge/amd/amdk8/early_ht.c"
113 static void sio_setup(void)
119 /* Subject decoding */
120 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
122 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
124 /* LPC Positive Decode 0 */
125 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
126 /* Serial 0, Serial 1 */
127 dword |= (1 << 0) | (1 << 1);
128 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
131 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
133 unsigned last_boot_normal_x = last_boot_normal();
135 /* Is this a CPU only reset? Or is this a secondary CPU? */
136 if ((cpu_init_detectedx) || (!boot_cpu())) {
137 if (last_boot_normal_x) {
144 /* Nothing special needs to be done to find bus 0 */
145 /* Allow the HT devices to be found */
146 enumerate_ht_chain();
150 /* Setup the ck804 */
153 /* Is this a deliberate reset by the BIOS? */
154 if (bios_reset_detected() && last_boot_normal_x) {
158 /* This is the primary CPU. How should I boot? */
159 else if (do_normal_boot()) {
166 __asm__ volatile ("jmp __normal_image"
168 :"a" (bist), "b"(cpu_init_detectedx) /* inputs */
173 #if HAVE_FAILOVER_BOOT == 1
174 __asm__ volatile ("jmp __fallback_image"
176 :"a" (bist), "b"(cpu_init_detectedx) /* inputs */
182 #endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */
184 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
186 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
188 #if HAVE_FAILOVER_BOOT == 1
189 #if USE_FAILOVER_IMAGE == 1
190 failover_process(bist, cpu_init_detectedx);
192 real_main(bist, cpu_init_detectedx);
195 #if USE_FALLBACK_IMAGE == 1
196 failover_process(bist, cpu_init_detectedx);
198 real_main(bist, cpu_init_detectedx);
202 #if USE_FAILOVER_IMAGE == 0
203 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
205 static const uint16_t spd_addr[] = {
206 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
207 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
208 #if CONFIG_MAX_PHYSICAL_CPUS > 1
209 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
210 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
215 unsigned bsp_apicid = 0;
217 struct mem_controller ctrl[8];
221 bsp_apicid = init_cpus(cpu_init_detectedx);
224 it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
228 /* Halt if there was a built in self test failure */
229 report_bist_failure(bist);
232 dump_pci_device(PCI_DEV(0, 0x18, 0));
235 needs_reset = setup_coherent_ht_domain();
237 wait_all_core0_started();
238 #if CONFIG_LOGICAL_CPUS==1
239 // It is said that we should start core1 after all core0 launched
241 wait_all_other_cores_started(bsp_apicid);
244 needs_reset |= ht_setup_chains_x();
246 needs_reset |= ck804_early_setup_x();
249 print_info("ht reset -\r\n");
253 allow_all_aps_stop(bsp_apicid);
256 //It's the time to set ctrl now;
257 fill_mem_ctrl(nodes, ctrl, spd_addr);
262 dump_spd_registers(&ctrl[0]);
263 dump_smbus_registers();
267 sdram_initialize(nodes, ctrl);
276 #endif /* USE_FAILOVER_IMAGE */