2 ## This file is part of the LinuxBIOS project.
4 ## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
5 ## (Thanks to LSRA University of Mannheim for their support)
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 uses USE_FALLBACK_IMAGE
25 uses USE_FAILOVER_IMAGE
26 uses HAVE_FALLBACK_BOOT
27 uses HAVE_FAILOVER_BOOT
30 uses HAVE_OPTION_TABLE
32 uses CONFIG_MAX_PHYSICAL_CPUS
33 uses CONFIG_LOGICAL_CPUS
42 uses ROM_SECTION_OFFSET
43 uses CONFIG_ROM_PAYLOAD
44 uses CONFIG_ROM_PAYLOAD_START
45 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
53 uses LB_CKS_RANGE_START
56 uses MAINBOARD_PART_NUMBER
59 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
60 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
61 uses LINUXBIOS_EXTRA_VERSION
71 uses DEFAULT_CONSOLE_LOGLEVEL
72 uses MAXIMUM_CONSOLE_LOGLEVEL
73 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
74 uses CONFIG_CONSOLE_SERIAL8250
75 uses CONFIG_CONSOLE_BTEXT
79 uses CONFIG_CONSOLE_VGA
80 uses CONFIG_PCI_ROM_RUN
81 uses HW_MEM_HOLE_SIZEK
87 uses DCACHE_RAM_GLOBAL_VAR_SIZE
88 uses CONFIG_AP_CODE_IN_CAR
90 uses WAIT_BEFORE_CPUS_INIT
92 uses ENABLE_APIC_EXT_ID
96 uses CONFIG_PCI_64BIT_PREF_MEM
98 uses HT_CHAIN_UNITID_BASE
99 uses HT_CHAIN_END_UNITID_BASE
100 uses SB_HT_CHAIN_ON_BUS0
101 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
103 uses CONFIG_LB_MEM_TOPK
106 ## ROM_SIZE is the size of boot ROM that this board will use.
108 default ROM_SIZE=(512*1024)
111 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
113 default FALLBACK_SIZE=(252*1024)
116 default FAILOVER_SIZE=(4*1024)
123 ## Build code for the fallback boot
125 default HAVE_FALLBACK_BOOT=1
126 default HAVE_FAILOVER_BOOT=1
129 ## Build code to reset the motherboard from linuxBIOS
131 default HAVE_HARD_RESET=1
134 ## Build code to export a programmable irq routing table
136 default HAVE_PIRQ_TABLE=1
137 default IRQ_SLOT_COUNT=13
140 ## Build code to export an x86 MP table
141 ## Useful for specifying IRQ routing values
143 default HAVE_MP_TABLE=1
146 ## Build code to export a CMOS option table
148 default HAVE_OPTION_TABLE=1
151 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
153 default LB_CKS_RANGE_START=49
154 default LB_CKS_RANGE_END=122
155 default LB_CKS_LOC=123
158 ## Build code for SMP support
159 ## Only worry about 2 micro processors
162 default CONFIG_MAX_CPUS=2
163 default CONFIG_MAX_PHYSICAL_CPUS=1
164 default CONFIG_LOGICAL_CPUS=1
167 default HW_MEM_HOLE_SIZEK=0x100000
169 ##HT Unit ID offset, default is 1, the typical one
170 default HT_CHAIN_UNITID_BASE=0
172 ##real SB Unit ID, default is 0x20, mean dont touch it at last
173 #default HT_CHAIN_END_UNITID_BASE=0x10
175 #make the SB HT chain on bus 0, default is not (0)
176 default SB_HT_CHAIN_ON_BUS0=2
178 ##only offset for SB chain?, default is yes(1)
179 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
182 #default CONFIG_CONSOLE_BTEXT=1
185 default CONFIG_CONSOLE_VGA=1
186 default CONFIG_PCI_ROM_RUN=1
189 ## enable CACHE_AS_RAM specifics
191 default USE_DCACHE_RAM=1
192 #default DCACHE_RAM_BASE=0xcf000
193 #default DCACHE_RAM_SIZE=0x1000
194 default DCACHE_RAM_BASE=0xc8000
195 default DCACHE_RAM_SIZE=0x08000
196 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
197 default CONFIG_USE_INIT=0
199 default CONFIG_AP_CODE_IN_CAR=0
200 default MEM_TRAIN_SEQ=2
201 default WAIT_BEFORE_CPUS_INIT=0
204 #default ENABLE_APIC_EXT_ID=0
205 #default APIC_ID_OFFSET=0x10
206 #default LIFT_BSP_APIC_ID=0
209 #default CONFIG_PCI_64BIT_PREF_MEM=1
212 ## Build code to setup a generic IOAPIC
214 default CONFIG_IOAPIC=1
217 ## Clean up the motherboard id strings
219 default MAINBOARD_PART_NUMBER="A8NE"
220 default MAINBOARD_VENDOR="ASUS"
221 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
222 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
225 ### LinuxBIOS layout values
228 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
229 default ROM_IMAGE_SIZE = (64*1024)
233 ## Use a small 8K stack
235 default STACK_SIZE=0x2000
238 ## Use a small 16K heap
240 default HEAP_SIZE=0x4000
243 ## Only use the option table in a normal image
245 #efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
246 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
249 ## LinuxBIOS C code runs at this location in RAM
251 default _RAMBASE=0x00004000
254 ## Load the payload from the ROM
256 default CONFIG_ROM_PAYLOAD = 1
259 ### Defaults of options that you may want to override in the target config file
263 ## The default compiler
265 default CC="$(CROSS_COMPILE)gcc -m32"
269 ## Disable the gdb stub by default
271 default CONFIG_GDB_STUB=0
274 ## The Serial Console
277 # To Enable the Serial Console
278 default CONFIG_CONSOLE_SERIAL8250=1
280 ## Select the serial console baud rate
281 default TTYS0_BAUD=115200
282 #default TTYS0_BAUD=57600
283 #default TTYS0_BAUD=38400
284 #default TTYS0_BAUD=19200
285 #default TTYS0_BAUD=9600
286 #default TTYS0_BAUD=4800
287 #default TTYS0_BAUD=2400
288 #default TTYS0_BAUD=1200
290 # Select the serial console base port
291 default TTYS0_BASE=0x3f8
293 # Select the serial protocol
294 # This defaults to 8 data bits, 1 stop bit, and no parity
295 default TTYS0_LCS=0x3
298 ### Select the linuxBIOS loglevel
300 ## EMERG 1 system is unusable
301 ## ALERT 2 action must be taken immediately
302 ## CRIT 3 critical conditions
303 ## ERR 4 error conditions
304 ## WARNING 5 warning conditions
305 ## NOTICE 6 normal but significant condition
306 ## INFO 7 informational
307 ## DEBUG 8 debug-level messages
308 ## SPEW 9 Way too many details
310 ## Request this level of debugging output
311 default DEFAULT_CONSOLE_LOGLEVEL=8
312 ## At a maximum only compile in this level of debugging
313 default MAXIMUM_CONSOLE_LOGLEVEL=8
316 ## Select power on after power fail setting
317 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"