src/mainboard/asus/a8n_e/Config.lb

   1 ##
   2 ## This file is part of the LinuxBIOS project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6 ## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
   7 ## (Thanks to LSRA University of Mannheim for their support)
   8 ##
   9 ## This program is free software; you can redistribute it and/or modify
  10 ## it under the terms of the GNU General Public License as published by
  11 ## the Free Software Foundation; either version 2 of the License, or
  12 ## (at your option) any later version.
  13 ##
  14 ## This program is distributed in the hope that it will be useful,
  15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ## GNU General Public License for more details.
  18 ##
  19 ## You should have received a copy of the GNU General Public License
  20 ## along with this program; if not, write to the Free Software
  21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 ##
  23
  24 ##
  25 ## Compute the location and size of where this firmware image
  26 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
  27 ##
  28 if USE_FAILOVER_IMAGE
  29         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  30         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  31 else
  32     if USE_FALLBACK_IMAGE
  33         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  34         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35     else
  36         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  37         default ROM_SECTION_OFFSET = 0
  38     end
  39 end
  40
  41 ##
  42 ## Compute the start location and size size of
  43 ## The linuxBIOS bootloader.
  44 ##
  45 default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  46 default CONFIG_ROM_PAYLOAD_START = ( 0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1 )
  47
  48 ##
  49 ## Compute where this copy of linuxBIOS will start in the boot rom
  50 ##
  51 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  52
  53 ##
  54 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  55 ## execution speed.
  56 ##
  57 ## XIP_ROM_SIZE must be a power of 2.  (here 64 Kbyte)
  58 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  59 ##
  60 default XIP_ROM_SIZE = ( 64 * 1024 )
  61
  62 if USE_FAILOVER_IMAGE
  63         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
  64 else
  65     if USE_FALLBACK_IMAGE
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE )
  67     else
  68         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
  69     end
  70 end
  71
  72 arch i386 end
  73
  74 ##
  75 ## Build the objects we have code for in this directory.
  76 ##
  77
  78 driver mainboard.o
  79
  80 #dir /drivers/ati/ragexl
  81
  82 # Needed by irq_tables and mptable and acpi_tables.
  83 object get_bus_conf.o
  84
  85 if HAVE_MP_TABLE
  86         object mptable.o
  87 end
  88
  89 if HAVE_PIRQ_TABLE
  90         object irq_tables.o
  91 end
  92
  93 if USE_DCACHE_RAM
  94         if CONFIG_USE_INIT
  95                 makerule ./auto.o
  96                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  97                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
  98                 end
  99         else
 100                 makerule ./auto.inc
 101                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 102                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
 103                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
 104                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 105                 end
 106         end
 107 end
 108
 109 ##
 110 ## Build our 16 bit and 32 bit linuxBIOS entry code
 111 ##
 112 if HAVE_FAILOVER_BOOT
 113     if USE_FAILOVER_IMAGE
 114         mainboardinit cpu/x86/16bit/entry16.inc
 115         ldscript /cpu/x86/16bit/entry16.lds
 116     end
 117 else
 118     if USE_FALLBACK_IMAGE
 119         mainboardinit cpu/x86/16bit/entry16.inc
 120         ldscript /cpu/x86/16bit/entry16.lds
 121     end
 122 end
 123
 124 mainboardinit cpu/x86/32bit/entry32.inc
 125
 126 if USE_DCACHE_RAM
 127         if CONFIG_USE_INIT
 128                 ldscript /cpu/x86/32bit/entry32.lds
 129         end
 130
 131         if CONFIG_USE_INIT
 132                 ldscript /cpu/amd/car/cache_as_ram.lds
 133         end
 134 end
 135
 136 ##
 137 ## Build our reset vector (This is where linuxBIOS is entered)
 138 ##
 139 if HAVE_FAILOVER_BOOT
 140     if USE_FAILOVER_IMAGE
 141         mainboardinit cpu/x86/16bit/reset16.inc
 142         ldscript /cpu/x86/16bit/reset16.lds
 143     else
 144         mainboardinit cpu/x86/32bit/reset32.inc
 145         ldscript /cpu/x86/32bit/reset32.lds
 146     end
 147 else
 148     if USE_FALLBACK_IMAGE
 149         mainboardinit cpu/x86/16bit/reset16.inc
 150         ldscript /cpu/x86/16bit/reset16.lds
 151     else
 152         mainboardinit cpu/x86/32bit/reset32.inc
 153         ldscript /cpu/x86/32bit/reset32.lds
 154     end
 155 end
 156
 157 if USE_DCACHE_RAM
 158 else
 159         ### Should this be in the northbridge code?
 160         mainboardinit arch/i386/lib/cpu_reset.inc
 161 end
 162
 163 ##
 164 ## Include an id string (For safe flashing)
 165 ##
 166 mainboardinit southbridge/nvidia/ck804/id.inc
 167 ldscript /southbridge/nvidia/ck804/id.lds
 168
 169 ##
 170 ## ROMSTRAP table for CK804
 171 ##
 172 if HAVE_FAILOVER_BOOT
 173         if USE_FAILOVER_IMAGE
 174                 mainboardinit southbridge/nvidia/ck804/romstrap.inc
 175                 ldscript /southbridge/nvidia/ck804/romstrap.lds
 176         end
 177 else
 178         if USE_FALLBACK_IMAGE
 179                 mainboardinit southbridge/nvidia/ck804/romstrap.inc
 180                 ldscript /southbridge/nvidia/ck804/romstrap.lds
 181         end
 182 end
 183
 184 if USE_DCACHE_RAM
 185         ##
 186         ## Setup Cache-As-Ram
 187         ##
 188         mainboardinit cpu/amd/car/cache_as_ram.inc
 189 end
 190
 191
 192 ###
 193 ### This is the early phase of linuxBIOS startup
 194 ### Things are delicate and we test to see if we should
 195 ### failover to another image.
 196 ###
 197 if HAVE_FAILOVER_BOOT
 198     if USE_FAILOVER_IMAGE
 199         if USE_DCACHE_RAM
 200                 ldscript /arch/i386/lib/failover_failover.lds
 201         end
 202     end
 203 else
 204     if USE_FALLBACK_IMAGE
 205         if USE_DCACHE_RAM
 206                 ldscript /arch/i386/lib/failover.lds
 207         end
 208     end
 209 end
 210
 211 ###
 212 ### O.k. We aren't just an intermediary anymore!
 213 ###
 214
 215 ##
 216 ## Setup RAM
 217 ##
 218 if USE_DCACHE_RAM
 219         if CONFIG_USE_INIT
 220                 initobject auto.o
 221         else
 222                 mainboardinit ./auto.inc
 223         end
 224 end
 225
 226 ##
 227 ## Include the secondary configuration files
 228 ##
 229 if CONFIG_CHIP_NAME
 230         config chip.h
 231 end
 232
 233 chip northbridge/amd/amdk8/root_complex
 234         device apic_cluster 0 on
 235                 chip cpu/amd/socket_939
 236                         device apic 0 on end
 237                 end
 238         end
 239
 240         device pci_domain 0 on
 241                 chip northbridge/amd/amdk8 # mc0
 242                         device pci 18.0 on # northbridge
 243                                 # Devices on link 0, link 0 == LDT 0
 244                                 chip southbridge/nvidia/ck804
 245                                         device pci 0.0 on end # HT
 246                                         device pci 1.0 on # LPC
 247                                                 chip superio/ite/it8712f
 248                                                         device pnp 2e.0 off # Floppy
 249                                                                 io 0x60 = 0x03f0
 250                                                                 irq 0x70 = 6
 251                                                                 drq 0x74 = 2
 252                                                         end
 253                                                         device pnp 2e.1 on # Com1
 254                                                                 io 0x60 = 0x03f8
 255                                                                 irq 0x70 = 4
 256                                                         end
 257                                                         device pnp 2e.2 off # Com2
 258                                                                 io 0x60 = 0x02f8
 259                                                                 irq 0x70 = 3
 260                                                         end
 261                                                         device pnp 2e.3 on # Parallel Port
 262                                                                 io 0x60 = 0x0378
 263                                                                 irq 0x70 = 7
 264                                                         end
 265                                                         device pnp 2e.4 on # Environment Controller
 266                                                                 io 0x60 = 0x0290
 267                                                                 io 0x62 = 0x0000
 268                                                                 irq 0x70 = 0x00
 269                                                         end
 270                                                         device pnp 2e.5 on # Keyboard
 271                                                                 io 0x60 = 0x0060
 272                                                                 io 0x62 = 0x0064
 273                                                                 irq 0x70 = 0x01
 274                                                                 irq 0x71 = 0x02
 275                                                         end
 276                                                         device pnp 2e.6 on # Mouse
 277                                                                 irq 0x70 = 0x0c
 278                                                                 irq 0x71 = 0x02
 279                                                         end
 280                                                         device pnp 2e.7 on # GPIO config
 281                                                                 # Set GPIO 1 & 2
 282                                                                 io 0x25 = 0x0000
 283                                                                 # Set GPIO 3 & 4
 284                                                                 io 0x27 = 0x2540
 285                                                                 # GPIO Polarity for Set 3
 286                                                                 io 0xb2 = 0x2100
 287                                                                 # GPIO Pin Internal Pull up for Set 3
 288                                                                 io 0xba = 0x0100
 289                                                                 # Simple I/O register config
 290                                                                 io 0xc0 = 0x0000
 291                                                                 io 0xc2 = 0x2540
 292                                                                 io 0xc8 = 0x0000
 293                                                                 io 0xca = 0x0500
 294                                                         end
 295                                                         device pnp 2e.8 off end # Midi port
 296                                                         device pnp 2e.9 off end # Game port
 297                                                         device pnp 2e.a off end # IR
 298                                                 end
 299                                         end
 300                                         device pci 1.1 on # SM 0
 301                                                 # chip drivers/generic/generic #dimm 0-0-0
 302                                                 #       device i2c 50 on end
 303                                                 # end
 304                                                 # chip drivers/generic/generic #dimm 0-0-1
 305                                                 #       device i2c 51 on end
 306                                                 # end
 307                                                 # chip drivers/generic/generic #dimm 0-1-0
 308                                                 #       device i2c 52 on end
 309                                                 # end
 310                                                 # chip drivers/generic/generic #dimm 0-1-1
 311                                                 #       device i2c 53 on end
 312                                                 # end
 313                                                 # chip drivers/generic/generic #dimm 1-0-0
 314                                                 #       device i2c 54 on end
 315                                                 # end
 316                                                 # chip drivers/generic/generic #dimm 1-0-1
 317                                                 #       device i2c 55 on end
 318                                                 # end
 319                                                 # chip drivers/generic/generic #dimm 1-1-0
 320                                                 #       device i2c 56 on end
 321                                                 # end
 322                                                 # chip drivers/generic/generic #dimm 1-1-1
 323                                                 #       device i2c 57 on end
 324                                                 # end
 325                                         end # SM
 326                                         device pci 2.0 on end # USB 1.1
 327                                         device pci 2.1 on end # USB 2
 328                                         device pci 4.0 off end # ACI
 329                                         device pci 4.1 off end # MCI
 330                                         device pci 6.0 on end # IDE
 331                                         device pci 7.0 on end # SATA 1
 332                                         device pci 8.0 on end # SATA 0
 333                                         device pci 9.0 on end # PCI
 334                                         device pci a.0 on end # NIC
 335                                         device pci b.0 on end # PCI E 3
 336                                         device pci c.0 on end # PCI E 2
 337                                         device pci d.0 on end # PCI E 1
 338                                         device pci e.0 on end # PCI E 0
 339                                         register "ide0_enable" = "1"
 340                                         register "ide1_enable" = "1"
 341                                         register "sata0_enable" = "1"
 342                                         register "sata1_enable" = "1"
 343 #                                       register "mac_eeprom_smbus" = "3"
 344 #                                       register "mac_eeprom_addr" = "0x51"
 345                                 end
 346
 347                         end # device pci 18.0
 348                         device pci 18.1 on end
 349                         device pci 18.2 on end
 350                         device pci 18.3 on end
 351                 end # mc0
 352         end # pci_domain
 353 end # root_complex