2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 ## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 ## (Thanks to LSRA University of Mannheim for their support)
9 ## This program is free software; you can redistribute it and/or modify
10 ## it under the terms of the GNU General Public License as published by
11 ## the Free Software Foundation; either version 2 of the License, or
12 ## (at your option) any later version.
14 ## This program is distributed in the hope that it will be useful,
15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ## GNU General Public License for more details.
19 ## You should have received a copy of the GNU General Public License
20 ## along with this program; if not, write to the Free Software
21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 default ROM_SECTION_SIZE = FAILOVER_SIZE
26 default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
29 default ROM_SECTION_SIZE = FALLBACK_SIZE
30 default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
32 default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
33 default ROM_SECTION_OFFSET = 0
36 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
37 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
38 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
39 # XIP_ROM_SIZE must be a power of 2.
40 # XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE.
41 default XIP_ROM_SIZE = 64 * 1024
43 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
46 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
48 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
53 # Needed by irq_tables and mptable and acpi_tables.
55 if HAVE_MP_TABLE object mptable.o end
56 if HAVE_PIRQ_TABLE object irq_tables.o end
60 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
61 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
65 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
66 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
67 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
68 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
74 mainboardinit cpu/x86/16bit/entry16.inc
75 ldscript /cpu/x86/16bit/entry16.lds
79 mainboardinit cpu/x86/16bit/entry16.inc
80 ldscript /cpu/x86/16bit/entry16.lds
83 mainboardinit cpu/x86/32bit/entry32.inc
86 ldscript /cpu/x86/32bit/entry32.lds
87 ldscript /cpu/amd/car/cache_as_ram.lds
92 mainboardinit cpu/x86/16bit/reset16.inc
93 ldscript /cpu/x86/16bit/reset16.lds
95 mainboardinit cpu/x86/32bit/reset32.inc
96 ldscript /cpu/x86/32bit/reset32.lds
100 mainboardinit cpu/x86/16bit/reset16.inc
101 ldscript /cpu/x86/16bit/reset16.lds
103 mainboardinit cpu/x86/32bit/reset32.inc
104 ldscript /cpu/x86/32bit/reset32.lds
109 mainboardinit arch/i386/lib/cpu_reset.inc
111 # Include an ID string (for safe flashing).
112 mainboardinit southbridge/nvidia/ck804/id.inc
113 ldscript /southbridge/nvidia/ck804/id.lds
114 # ROMSTRAP table for CK804.
115 if HAVE_FAILOVER_BOOT
116 if USE_FAILOVER_IMAGE
117 mainboardinit southbridge/nvidia/ck804/romstrap.inc
118 ldscript /southbridge/nvidia/ck804/romstrap.lds
121 if USE_FALLBACK_IMAGE
122 mainboardinit southbridge/nvidia/ck804/romstrap.inc
123 ldscript /southbridge/nvidia/ck804/romstrap.lds
127 mainboardinit cpu/amd/car/cache_as_ram.inc
129 if HAVE_FAILOVER_BOOT
130 if USE_FAILOVER_IMAGE
132 ldscript /arch/i386/lib/failover_failover.lds
136 if USE_FALLBACK_IMAGE
138 ldscript /arch/i386/lib/failover.lds
146 mainboardinit ./auto.inc
153 chip northbridge/amd/amdk8/root_complex # Root complex
154 device apic_cluster 0 on # APIC cluster
155 chip cpu/amd/socket_939 # Socket 939 CPU
156 device apic 0 on end # APIC
160 device pci_domain 0 on # PCI domain
161 chip northbridge/amd/amdk8 # mc0
162 device pci 18.0 on # Northbridge
163 # Devices on link 0, link 0 == LDT 0
164 chip southbridge/nvidia/ck804 # Southbridge
165 device pci 0.0 on end # HT
166 device pci 1.0 on # LPC
167 chip superio/ite/it8712f # Super I/O
168 device pnp 2e.0 off # Floppy
173 device pnp 2e.1 on # Com1
177 device pnp 2e.2 off # Com2
181 device pnp 2e.3 on # Parallel port
185 device pnp 2e.4 on # Environment controller
190 device pnp 2e.5 on # PS/2 keyboard
196 device pnp 2e.6 on # PS/2 mouse
200 device pnp 2e.7 on # GPIO config
205 # GPIO Polarity for Set 3
207 # GPIO Pin Internal Pull up for Set 3
209 # Simple I/O register config
215 device pnp 2e.8 off end # Midi port
216 device pnp 2e.9 off end # Game port
217 device pnp 2e.a off end # IR
220 device pci 1.1 on # SM 0
221 # chip drivers/generic/generic #dimm 0-0-0
222 # device i2c 50 on end
224 # chip drivers/generic/generic #dimm 0-0-1
225 # device i2c 51 on end
227 # chip drivers/generic/generic #dimm 0-1-0
228 # device i2c 52 on end
230 # chip drivers/generic/generic #dimm 0-1-1
231 # device i2c 53 on end
233 # chip drivers/generic/generic #dimm 1-0-0
234 # device i2c 54 on end
236 # chip drivers/generic/generic #dimm 1-0-1
237 # device i2c 55 on end
239 # chip drivers/generic/generic #dimm 1-1-0
240 # device i2c 56 on end
242 # chip drivers/generic/generic #dimm 1-1-1
243 # device i2c 57 on end
246 device pci 2.0 on end # USB 1.1
247 device pci 2.1 on end # USB 2
248 device pci 4.0 off end # Onboard audio (ACI)
249 device pci 4.1 off end # Onboard modem (MCI)
250 device pci 6.0 on end # IDE
251 device pci 7.0 on end # SATA 1
252 device pci 8.0 on end # SATA 0
253 device pci 9.0 on end # PCI
254 device pci a.0 on end # NIC
255 device pci b.0 on end # PCI E 3
256 device pci c.0 on end # PCI E 2
257 device pci d.0 on end # PCI E 1
258 device pci e.0 on end # PCI E 0
259 register "ide0_enable" = "1"
260 register "ide1_enable" = "1"
261 register "sata0_enable" = "1"
262 register "sata1_enable" = "1"
263 # register "mac_eeprom_smbus" = "3"
264 # register "mac_eeprom_addr" = "0x51"
267 device pci 18.1 on end
268 device pci 18.2 on end
269 device pci 18.3 on end