2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
26 "E350M1 ", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
40 Name(HPBA, 0xFED00000) /* Base address of HPET table */
42 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44 /* USB overcurrent mapping pins. */
56 /* Some global data */
57 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
58 Name(OSV, Ones) /* Assume nothing */
59 Name(PMOD, One) /* Assume APIC */
65 Scope (\_PR) { /* define processor scope */
67 CPU0, /* name space name */
68 0, /* Unique number for this processor */
69 0x808, /* PBLK system I/O address !hardcoded! */
70 0x06 /* PBLKLEN for boot processor */
72 #include "acpi/cpstate.asl"
76 CPU1, /* name space name */
77 1, /* Unique number for this processor */
78 0x0000, /* PBLK system I/O address !hardcoded! */
79 0x00 /* PBLKLEN for boot processor */
81 #include "acpi/cpstate.asl"
85 /* PIC IRQ mapping registers, C00h-C01h. */
86 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
87 Field(PRQM, ByteAcc, NoLock, Preserve) {
89 PRQD, 0x00000008, /* Offset: 1h */
91 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
92 PIRA, 0x00000008, /* Index 0 */
93 PIRB, 0x00000008, /* Index 1 */
94 PIRC, 0x00000008, /* Index 2 */
95 PIRD, 0x00000008, /* Index 3 */
96 PIRE, 0x00000008, /* Index 4 */
97 PIRF, 0x00000008, /* Index 5 */
98 PIRG, 0x00000008, /* Index 6 */
99 PIRH, 0x00000008, /* Index 7 */
102 /* PCI Error control register */
103 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
104 Field(PERC, ByteAcc, NoLock, Preserve) {
111 /* Client Management index/data registers */
112 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
113 Field(CMT, ByteAcc, NoLock, Preserve) {
115 /* Client Management Data register */
123 /* GPM Port register */
124 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
125 Field(GPT, ByteAcc, NoLock, Preserve) {
136 /* Flash ROM program enable register */
137 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
138 Field(FRE, ByteAcc, NoLock, Preserve) {
143 /* PM2 index/data registers */
144 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
145 Field(PM2R, ByteAcc, NoLock, Preserve) {
150 /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
151 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
152 Field(PIOR, ByteAcc, NoLock, Preserve) {
156 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
157 Offset(0x00), /* MiscControl */
161 Offset(0x01), /* MiscStatus */
165 Offset(0x04), /* SmiWakeUpEventEnable3 */
168 Offset(0x07), /* SmiWakeUpEventStatus3 */
171 Offset(0x10), /* AcpiEnable */
174 Offset(0x1C), /* ProgramIoEnable */
181 Offset(0x1D), /* IOMonitorStatus */
188 Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */
190 Offset(0x36), /* GEvtLevelConfig */
194 Offset(0x37), /* GPMLevelConfig0 */
201 Offset(0x38), /* GPMLevelConfig1 */
208 Offset(0x3B), /* PMEStatus1 */
217 Offset(0x55), /* SoftPciRst */
225 /* Offset(0x61), */ /* Options_1 */
229 Offset(0x65), /* UsbPMControl */
232 Offset(0x68), /* MiscEnable68 */
236 Offset(0x92), /* GEVENTIN */
239 Offset(0x96), /* GPM98IN */
242 Offset(0x9A), /* EnhanceControl */
245 Offset(0xA8), /* PIO7654Enable */
250 Offset(0xA9), /* PIO7654Status */
258 * First word is PM1_Status, Second word is PM1_Enable
260 OperationRegion(P1EB, SystemIO, APEB, 0x04)
261 Field(P1EB, ByteAcc, NoLock, Preserve) {
286 /* PCIe Configuration Space for 16 busses */
287 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
288 Field(PCFG, ByteAcc, NoLock, Preserve) {
289 /* Byte offsets are computed using the following technique:
290 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
291 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
293 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
295 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
306 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
309 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
311 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
313 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
315 P92E, 1, /* Port92 decode enable */
318 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
319 Field(SB5, AnyAcc, NoLock, Preserve){
321 Offset(0x120), /* Port 0 Task file status */
327 Offset(0x128), /* Port 0 Serial ATA status */
331 Offset(0x12C), /* Port 0 Serial ATA control */
333 Offset(0x130), /* Port 0 Serial ATA error */
338 offset(0x1A0), /* Port 1 Task file status */
344 Offset(0x1A8), /* Port 1 Serial ATA status */
348 Offset(0x1AC), /* Port 1 Serial ATA control */
350 Offset(0x1B0), /* Port 1 Serial ATA error */
355 Offset(0x220), /* Port 2 Task file status */
361 Offset(0x228), /* Port 2 Serial ATA status */
365 Offset(0x22C), /* Port 2 Serial ATA control */
367 Offset(0x230), /* Port 2 Serial ATA error */
372 Offset(0x2A0), /* Port 3 Task file status */
378 Offset(0x2A8), /* Port 3 Serial ATA status */
382 Offset(0x2AC), /* Port 3 Serial ATA control */
384 Offset(0x2B0), /* Port 3 Serial ATA error */
391 #include "acpi/routing.asl"
397 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
399 if(CondRefOf(\_OSI,Local1))
401 Store(1, OSTP) /* Assume some form of XP */
402 if (\_OSI("Windows 2006")) /* Vista */
407 If(WCMP(\_OS,"Linux")) {
408 Store(3, OSTP) /* Linux */
410 Store(4, OSTP) /* Gotta be WinCE */
416 Method(_PIC, 0x01, NotSerialized)
424 Method(CIRQ, 0x00, NotSerialized){
435 Name(IRQB, ResourceTemplate(){
436 IRQ(Level,ActiveLow,Shared){15}
439 Name(IRQP, ResourceTemplate(){
440 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
443 Name(PITF, ResourceTemplate(){
444 IRQ(Level,ActiveLow,Exclusive){9}
448 Name(_HID, EISAID("PNP0C0F"))
453 Return(0x0B) /* sata is invisible */
455 Return(0x09) /* sata is disabled */
457 } /* End Method(_SB.INTA._STA) */
460 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
462 } /* End Method(_SB.INTA._DIS) */
465 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
467 } /* Method(_SB.INTA._PRS) */
470 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
471 CreateWordField(IRQB, 0x1, IRQN)
472 ShiftLeft(1, PIRA, IRQN)
474 } /* Method(_SB.INTA._CRS) */
477 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
478 CreateWordField(ARG0, 1, IRQM)
480 /* Use lowest available IRQ */
481 FindSetRightBit(IRQM, Local0)
486 } /* End Method(_SB.INTA._SRS) */
487 } /* End Device(INTA) */
490 Name(_HID, EISAID("PNP0C0F"))
495 Return(0x0B) /* sata is invisible */
497 Return(0x09) /* sata is disabled */
499 } /* End Method(_SB.INTB._STA) */
502 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
504 } /* End Method(_SB.INTB._DIS) */
507 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
509 } /* Method(_SB.INTB._PRS) */
512 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
513 CreateWordField(IRQB, 0x1, IRQN)
514 ShiftLeft(1, PIRB, IRQN)
516 } /* Method(_SB.INTB._CRS) */
519 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
520 CreateWordField(ARG0, 1, IRQM)
522 /* Use lowest available IRQ */
523 FindSetRightBit(IRQM, Local0)
528 } /* End Method(_SB.INTB._SRS) */
529 } /* End Device(INTB) */
532 Name(_HID, EISAID("PNP0C0F"))
537 Return(0x0B) /* sata is invisible */
539 Return(0x09) /* sata is disabled */
541 } /* End Method(_SB.INTC._STA) */
544 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
546 } /* End Method(_SB.INTC._DIS) */
549 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
551 } /* Method(_SB.INTC._PRS) */
554 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
555 CreateWordField(IRQB, 0x1, IRQN)
556 ShiftLeft(1, PIRC, IRQN)
558 } /* Method(_SB.INTC._CRS) */
561 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
562 CreateWordField(ARG0, 1, IRQM)
564 /* Use lowest available IRQ */
565 FindSetRightBit(IRQM, Local0)
570 } /* End Method(_SB.INTC._SRS) */
571 } /* End Device(INTC) */
574 Name(_HID, EISAID("PNP0C0F"))
579 Return(0x0B) /* sata is invisible */
581 Return(0x09) /* sata is disabled */
583 } /* End Method(_SB.INTD._STA) */
586 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
588 } /* End Method(_SB.INTD._DIS) */
591 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
593 } /* Method(_SB.INTD._PRS) */
596 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
597 CreateWordField(IRQB, 0x1, IRQN)
598 ShiftLeft(1, PIRD, IRQN)
600 } /* Method(_SB.INTD._CRS) */
603 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
604 CreateWordField(ARG0, 1, IRQM)
606 /* Use lowest available IRQ */
607 FindSetRightBit(IRQM, Local0)
612 } /* End Method(_SB.INTD._SRS) */
613 } /* End Device(INTD) */
616 Name(_HID, EISAID("PNP0C0F"))
621 Return(0x0B) /* sata is invisible */
623 Return(0x09) /* sata is disabled */
625 } /* End Method(_SB.INTE._STA) */
628 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
630 } /* End Method(_SB.INTE._DIS) */
633 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
635 } /* Method(_SB.INTE._PRS) */
638 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
639 CreateWordField(IRQB, 0x1, IRQN)
640 ShiftLeft(1, PIRE, IRQN)
642 } /* Method(_SB.INTE._CRS) */
645 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
646 CreateWordField(ARG0, 1, IRQM)
648 /* Use lowest available IRQ */
649 FindSetRightBit(IRQM, Local0)
654 } /* End Method(_SB.INTE._SRS) */
655 } /* End Device(INTE) */
658 Name(_HID, EISAID("PNP0C0F"))
663 Return(0x0B) /* sata is invisible */
665 Return(0x09) /* sata is disabled */
667 } /* End Method(_SB.INTF._STA) */
670 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
672 } /* End Method(_SB.INTF._DIS) */
675 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
677 } /* Method(_SB.INTF._PRS) */
680 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
681 CreateWordField(IRQB, 0x1, IRQN)
682 ShiftLeft(1, PIRF, IRQN)
684 } /* Method(_SB.INTF._CRS) */
687 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
688 CreateWordField(ARG0, 1, IRQM)
690 /* Use lowest available IRQ */
691 FindSetRightBit(IRQM, Local0)
696 } /* End Method(_SB.INTF._SRS) */
697 } /* End Device(INTF) */
700 Name(_HID, EISAID("PNP0C0F"))
705 Return(0x0B) /* sata is invisible */
707 Return(0x09) /* sata is disabled */
709 } /* End Method(_SB.INTG._STA) */
712 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
714 } /* End Method(_SB.INTG._DIS) */
717 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
719 } /* Method(_SB.INTG._CRS) */
722 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
723 CreateWordField(IRQB, 0x1, IRQN)
724 ShiftLeft(1, PIRG, IRQN)
726 } /* Method(_SB.INTG._CRS) */
729 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
730 CreateWordField(ARG0, 1, IRQM)
732 /* Use lowest available IRQ */
733 FindSetRightBit(IRQM, Local0)
738 } /* End Method(_SB.INTG._SRS) */
739 } /* End Device(INTG) */
742 Name(_HID, EISAID("PNP0C0F"))
747 Return(0x0B) /* sata is invisible */
749 Return(0x09) /* sata is disabled */
751 } /* End Method(_SB.INTH._STA) */
754 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
756 } /* End Method(_SB.INTH._DIS) */
759 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
761 } /* Method(_SB.INTH._CRS) */
764 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
765 CreateWordField(IRQB, 0x1, IRQN)
766 ShiftLeft(1, PIRH, IRQN)
768 } /* Method(_SB.INTH._CRS) */
771 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
772 CreateWordField(ARG0, 1, IRQM)
774 /* Use lowest available IRQ */
775 FindSetRightBit(IRQM, Local0)
780 } /* End Method(_SB.INTH._SRS) */
781 } /* End Device(INTH) */
783 } /* End Scope(_SB) */
786 /* Supported sleep states: */
787 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
789 If (LAnd(SSFG, 0x01)) {
790 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
792 If (LAnd(SSFG, 0x02)) {
793 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
795 If (LAnd(SSFG, 0x04)) {
796 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
798 If (LAnd(SSFG, 0x08)) {
799 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
802 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
804 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
805 Name(CSMS, 0) /* Current System State */
807 /* Wake status package */
808 Name(WKST,Package(){Zero, Zero})
811 * \_PTS - Prepare to Sleep method
814 * Arg0=The value of the sleeping state S1=1, S2=2, etc
819 * The _PTS control method is executed at the beginning of the sleep process
820 * for S1-S5. The sleeping value is passed to the _PTS control method. This
821 * control method may be executed a relatively long time before entering the
822 * sleep state and the OS may abort the operation without notification to
823 * the ACPI driver. This method cannot modify the configuration or power
824 * state of any device in the system.
827 /* DBGO("\\_PTS\n") */
828 /* DBGO("From S0 to S") */
832 /* Don't allow PCIRST# to reset USB */
837 /* Clear sleep SMI status flag and enable sleep SMI trap. */
841 /* On older chips, clear PciExpWakeDisEn */
842 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
847 /* Clear wake status structure. */
848 Store(0, Index(WKST,0))
849 Store(0, Index(WKST,1))
850 } /* End Method(\_PTS) */
853 * The following method results in a "not a valid reserved NameSeg"
854 * warning so I have commented it out for the duration. It isn't
855 * used, so it could be removed.
858 * \_GTS OEM Going To Sleep method
861 * Arg0=The value of the sleeping state S1=1, S2=2
868 * DBGO("From S0 to S")
875 * \_BFS OEM Back From Sleep method
878 * Arg0=The value of the sleeping state S1=1, S2=2
884 /* DBGO("\\_BFS\n") */
887 /* DBGO(" to S0\n") */
891 * \_WAK System Wake method
894 * Arg0=The value of the sleeping state S1=1, S2=2
897 * Return package of 2 DWords
899 * 0x00000000 wake succeeded
900 * 0x00000001 Wake was signaled but failed due to lack of power
901 * 0x00000002 Wake was signaled but failed due to thermal condition
902 * Dword 2 - Power Supply state
903 * if non-zero the effective S-state the power supply entered
906 /* DBGO("\\_WAK\n") */
909 /* DBGO(" to S0\n") */
914 /* Restore PCIRST# so it resets USB */
919 /* Arbitrarily clear PciExpWakeStatus */
922 /* if(DeRefOf(Index(WKST,0))) {
923 * Store(0, Index(WKST,1))
925 * Store(Arg0, Index(WKST,1))
929 } /* End Method(\_WAK) */
931 Scope(\_GPE) { /* Start Scope GPE */
932 /* General event 0 */
934 * DBGO("\\_GPE\\_L00\n")
938 /* General event 1 */
940 * DBGO("\\_GPE\\_L00\n")
944 /* General event 2 */
946 * DBGO("\\_GPE\\_L00\n")
950 /* General event 3 */
952 /* DBGO("\\_GPE\\_L00\n") */
953 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
956 /* General event 4 */
958 * DBGO("\\_GPE\\_L00\n")
962 /* General event 5 */
964 * DBGO("\\_GPE\\_L00\n")
968 /* General event 6 - Used for GPM6, moved to USB.asl */
970 * DBGO("\\_GPE\\_L00\n")
974 /* General event 7 - Used for GPM7, moved to USB.asl */
976 * DBGO("\\_GPE\\_L07\n")
980 /* Legacy PM event */
982 /* DBGO("\\_GPE\\_L08\n") */
985 /* Temp warning (TWarn) event */
987 /* DBGO("\\_GPE\\_L09\n") */
988 /* Notify (\_TZ.TZ00, 0x80) */
993 * DBGO("\\_GPE\\_L0A\n")
997 /* USB controller PME# */
999 /* DBGO("\\_GPE\\_L0B\n") */
1000 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1001 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1002 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1003 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1004 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1005 Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
1006 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1007 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1010 /* AC97 controller PME# */
1012 * DBGO("\\_GPE\\_L0C\n")
1016 /* OtherTherm PME# */
1018 * DBGO("\\_GPE\\_L0D\n")
1022 /* GPM9 SCI event - Moved to USB.asl */
1024 * DBGO("\\_GPE\\_L0E\n")
1028 /* PCIe HotPlug event */
1030 * DBGO("\\_GPE\\_L0F\n")
1034 /* ExtEvent0 SCI event */
1036 /* DBGO("\\_GPE\\_L10\n") */
1040 /* ExtEvent1 SCI event */
1042 /* DBGO("\\_GPE\\_L11\n") */
1045 /* PCIe PME# event */
1047 * DBGO("\\_GPE\\_L12\n")
1051 /* GPM0 SCI event - Moved to USB.asl */
1053 * DBGO("\\_GPE\\_L13\n")
1057 /* GPM1 SCI event - Moved to USB.asl */
1059 * DBGO("\\_GPE\\_L14\n")
1063 /* GPM2 SCI event - Moved to USB.asl */
1065 * DBGO("\\_GPE\\_L15\n")
1069 /* GPM3 SCI event - Moved to USB.asl */
1071 * DBGO("\\_GPE\\_L16\n")
1075 /* GPM8 SCI event - Moved to USB.asl */
1077 * DBGO("\\_GPE\\_L17\n")
1081 /* GPIO0 or GEvent8 event */
1083 /* DBGO("\\_GPE\\_L18\n") */
1084 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1085 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1086 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1087 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1088 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1089 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1092 /* GPM4 SCI event - Moved to USB.asl */
1094 * DBGO("\\_GPE\\_L19\n")
1098 /* GPM5 SCI event - Moved to USB.asl */
1100 * DBGO("\\_GPE\\_L1A\n")
1104 /* Azalia SCI event */
1106 /* DBGO("\\_GPE\\_L1B\n") */
1107 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1108 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1111 /* GPM6 SCI event - Reassigned to _L06 */
1113 * DBGO("\\_GPE\\_L1C\n")
1117 /* GPM7 SCI event - Reassigned to _L07 */
1119 * DBGO("\\_GPE\\_L1D\n")
1123 /* GPIO2 or GPIO66 SCI event */
1125 * DBGO("\\_GPE\\_L1E\n")
1129 /* SATA SCI event - Moved to sata.asl */
1131 * DBGO("\\_GPE\\_L1F\n")
1135 } /* End Scope GPE */
1137 #include "acpi/usb.asl"
1140 Scope(\_SB) { /* Start \_SB scope */
1141 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1144 /* Note: Only need HID on Primary Bus */
1148 Name(_HID, EISAID("PNP0A03"))
1149 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1150 Method(_BBN, 0) { /* Bus number = 0 */
1154 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1155 Return(0x0B) /* Status is visible */
1159 If(PMOD){ Return(APR0) } /* APIC mode */
1160 Return (PR0) /* PIC Mode */
1163 /* Describe the Northbridge devices */
1165 Name(_ADR, 0x00000000)
1168 /* The internal GFX bridge */
1170 Name(_ADR, 0x00010000)
1171 Name(_PRW, Package() {0x18, 4})
1177 /* The external GFX bridge */
1179 Name(_ADR, 0x00020000)
1180 Name(_PRW, Package() {0x18, 4})
1182 If(PMOD){ Return(APS2) } /* APIC mode */
1183 Return (PS2) /* PIC Mode */
1187 /* Dev3 is also an external GFX bridge, not used in Herring */
1190 Name(_ADR, 0x00040000)
1191 Name(_PRW, Package() {0x18, 4})
1193 If(PMOD){ Return(APS4) } /* APIC mode */
1194 Return (PS4) /* PIC Mode */
1199 Name(_ADR, 0x00050000)
1200 Name(_PRW, Package() {0x18, 4})
1202 If(PMOD){ Return(APS5) } /* APIC mode */
1203 Return (PS5) /* PIC Mode */
1208 Name(_ADR, 0x00060000)
1209 Name(_PRW, Package() {0x18, 4})
1211 If(PMOD){ Return(APS6) } /* APIC mode */
1212 Return (PS6) /* PIC Mode */
1216 /* The onboard EtherNet chip */
1218 Name(_ADR, 0x00070000)
1219 Name(_PRW, Package() {0x18, 4})
1221 If(PMOD){ Return(APS7) } /* APIC mode */
1222 Return (PS7) /* PIC Mode */
1228 Name(_ADR, 0x00090000)
1229 Name(_PRW, Package() {0x18, 4})
1231 If(PMOD){ Return(APS9) } /* APIC mode */
1232 Return (PS9) /* PIC Mode */
1237 Name(_ADR, 0x000A0000)
1238 Name(_PRW, Package() {0x18, 4})
1240 If(PMOD){ Return(APSa) } /* APIC mode */
1241 Return (PSa) /* PIC Mode */
1246 Name(_ADR, 0x00150000)
1247 Name(_PRW, Package() {0x18, 4})
1249 If(PMOD){ Return(APE0) } /* APIC mode */
1250 Return (PE0) /* PIC Mode */
1254 Name(_ADR, 0x00150001)
1255 Name(_PRW, Package() {0x18, 4})
1257 If(PMOD){ Return(APE1) } /* APIC mode */
1258 Return (PE1) /* PIC Mode */
1262 Name(_ADR, 0x00150002)
1263 Name(_PRW, Package() {0x18, 4})
1265 If(PMOD){ Return(APE2) } /* APIC mode */
1266 Return (APE2) /* PIC Mode */
1270 Name(_ADR, 0x00150003)
1271 Name(_PRW, Package() {0x18, 4})
1273 If(PMOD){ Return(APE3) } /* APIC mode */
1274 Return (PE3) /* PIC Mode */
1278 /* PCI slot 1, 2, 3 */
1280 Name(_ADR, 0x00140004)
1281 Name(_PRW, Package() {0x18, 4})
1288 /* Describe the Southbridge devices */
1290 Name(_ADR, 0x00110000)
1291 #include "acpi/sata.asl"
1295 Name(_ADR, 0x00120000)
1296 Name(_PRW, Package() {0x0B, 3})
1300 Name(_ADR, 0x00120002)
1301 Name(_PRW, Package() {0x0B, 3})
1305 Name(_ADR, 0x00130000)
1306 Name(_PRW, Package() {0x0B, 3})
1310 Name(_ADR, 0x00130002)
1311 Name(_PRW, Package() {0x0B, 3})
1315 Name(_ADR, 0x00160000)
1316 Name(_PRW, Package() {0x0B, 3})
1320 Name(_ADR, 0x00160002)
1321 Name(_PRW, Package() {0x0B, 3})
1325 Name(_ADR, 0x00140005)
1326 Name(_PRW, Package() {0x0B, 3})
1330 Name(_ADR, 0x00140000)
1333 /* Primary (and only) IDE channel */
1335 Name(_ADR, 0x00140001)
1336 #include "acpi/ide.asl"
1340 Name(_ADR, 0x00140002)
1341 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1342 Field(AZPD, AnyAcc, NoLock, Preserve) {
1366 If(LEqual(OSTP,3)){ /* If we are running Linux */
1375 Name(_ADR, 0x00140003)
1377 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1378 } */ /* End Method(_SB.SBRDG._INI) */
1380 /* Real Time Clock Device */
1382 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1383 Name(_CRS, ResourceTemplate() {
1385 IO(Decode16,0x0070, 0x0070, 0, 2)
1386 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1388 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1390 Device(TMR) { /* Timer */
1391 Name(_HID,EISAID("PNP0100")) /* System Timer */
1392 Name(_CRS, ResourceTemplate() {
1394 IO(Decode16, 0x0040, 0x0040, 0, 4)
1395 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1397 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1399 Device(SPKR) { /* Speaker */
1400 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1401 Name(_CRS, ResourceTemplate() {
1402 IO(Decode16, 0x0061, 0x0061, 0, 1)
1404 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1407 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1408 Name(_CRS, ResourceTemplate() {
1410 IO(Decode16,0x0020, 0x0020, 0, 2)
1411 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1412 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1413 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1415 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1417 Device(MAD) { /* 8257 DMA */
1418 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1419 Name(_CRS, ResourceTemplate() {
1420 DMA(Compatibility,BusMaster,Transfer8){4}
1421 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1422 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1423 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1424 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1425 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1426 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1427 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1428 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1431 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1432 Name(_CRS, ResourceTemplate() {
1433 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1436 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1439 Name(_HID,EISAID("PNP0103"))
1440 Name(CRS,ResourceTemplate() {
1441 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1444 Return(0x0F) /* sata is visible */
1447 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1451 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1456 Name(_ADR, 0x00140004)
1457 } /* end HostPciBr */
1460 Name(_ADR, 0x00140005)
1461 } /* end Ac97audio */
1464 Name(_ADR, 0x00140006)
1465 } /* end Ac97modem */
1467 Name(CRES, ResourceTemplate() {
1468 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1470 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1471 0x0000, /* address granularity */
1472 0x0000, /* range minimum */
1473 0x0CF7, /* range maximum */
1474 0x0000, /* translation */
1478 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1479 0x0000, /* address granularity */
1480 0x0D00, /* range minimum */
1481 0xFFFF, /* range maximum */
1482 0x0000, /* translation */
1486 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1488 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1489 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1491 /* DRAM Memory from 1MB to TopMem */
1492 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1494 /* BIOS space just below 4GB */
1496 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1497 0x00, /* Granularity */
1498 0x00000000, /* Min */
1499 0x00000000, /* Max */
1500 0x00000000, /* Translation */
1501 0x00000001, /* Max-Min, RLEN */
1506 /* DRAM memory from 4GB to TopMem2 */
1507 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1508 0x00000000, /* Granularity */
1509 0x00000000, /* Min */
1510 0x00000000, /* Max */
1511 0x00000000, /* Translation */
1512 0x00000001, /* Max-Min, RLEN */
1517 /* BIOS space just below 16EB */
1518 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1519 0x00000000, /* Granularity */
1520 0x00000000, /* Min */
1521 0x00000000, /* Max */
1522 0x00000000, /* Translation */
1523 0x00000001, /* Max-Min, RLEN */
1528 /* memory space for PCI BARs below 4GB */
1529 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1530 }) /* End Name(_SB.PCI0.CRES) */
1533 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1535 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1536 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1537 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1538 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1539 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1540 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1542 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1543 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1544 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1545 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1547 If(LGreater(LOMH, 0xC0000)){
1548 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1549 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1552 /* Set size of memory from 1MB to TopMem */
1553 Subtract(TOM1, 0x100000, DMLL)
1556 * If(LNotEqual(TOM2, 0x00000000)){
1557 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1558 * Subtract(TOM2, 0x100000000, DMHL)
1562 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1563 If(LEqual(TOM2, 0x00000000)){
1564 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1567 Else { /* Otherwise, put the BIOS just below 16EB */
1568 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1572 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1573 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1575 * Declare memory between TOM1 and 4GB as available
1577 * Use ShiftLeft to avoid 64bit constant (for XP).
1578 * This will work even if the OS does 32bit arithmetic, as
1579 * 32bit (0x00000000 - TOM1) will wrap and give the same
1580 * result as 64bit (0x100000000 - TOM1).
1583 ShiftLeft(0x10000000, 4, Local0)
1584 Subtract(Local0, TOM1, Local0)
1587 Return(CRES) /* note to change the Name buffer */
1588 } /* end of Method(_SB.PCI0._CRS) */
1592 * FIRST METHOD CALLED UPON BOOT
1594 * 1. If debugging, print current OS and ACPI interpreter.
1595 * 2. Get PCI Interrupt routing from ACPI VSM, this
1596 * value is based on user choice in BIOS setup.
1599 /* DBGO("\\_SB\\_INI\n") */
1600 /* DBGO(" DSDT.ASL code from ") */
1601 /* DBGO(__DATE__) */
1603 /* DBGO(__TIME__) */
1604 /* DBGO("\n Sleep states supported: ") */
1606 /* DBGO(" \\_OS=") */
1608 /* DBGO("\n \\_REV=") */
1612 /* Determine the OS we're running on */
1615 /* On older chips, clear PciExpWakeDisEn */
1616 /*if (LLessEqual(\SBRI, 0x13)) {
1620 } /* End Method(_SB._INI) */
1621 } /* End Device(PCI0) */
1623 Device(PWRB) { /* Start Power button device */
1624 Name(_HID, EISAID("PNP0C0C"))
1626 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1627 Name(_STA, 0x0B) /* sata is invisible */
1629 } /* End \_SB scope */
1633 /* DBGO("\\_SI\\_SST\n") */
1634 /* DBGO(" New Indicator state: ") */
1638 } /* End Scope SI */
1642 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1643 Field (SMB0, ByteAcc, NoLock, Preserve) {
1644 HSTS, 8, /* SMBUS status */
1645 SSTS, 8, /* SMBUS slave status */
1646 HCNT, 8, /* SMBUS control */
1647 HCMD, 8, /* SMBUS host cmd */
1648 HADD, 8, /* SMBUS address */
1649 DAT0, 8, /* SMBUS data0 */
1650 DAT1, 8, /* SMBUS data1 */
1651 BLKD, 8, /* SMBUS block data */
1652 SCNT, 8, /* SMBUS slave control */
1653 SCMD, 8, /* SMBUS shaow cmd */
1654 SEVT, 8, /* SMBUS slave event */
1655 SDAT, 8 /* SMBUS slave data */
1658 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1660 Store (0xFA, Local0)
1661 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1669 Method (SWTC, 1, NotSerialized) {
1670 Store (Arg0, Local0)
1671 Store (0x07, Local2)
1673 While (LEqual (Local1, One)) {
1674 Store (And (HSTS, 0x1E), Local3)
1675 If (LNotEqual (Local3, Zero)) { /* read sucess */
1676 If (LEqual (Local3, 0x02)) {
1677 Store (Zero, Local2)
1680 Store (Zero, Local1)
1683 If (LLess (Local0, 0x0A)) { /* read failure */
1684 Store (0x10, Local2)
1685 Store (Zero, Local1)
1688 Sleep (0x0A) /* 10 ms, try again */
1689 Subtract (Local0, 0x0A, Local0)
1697 Method (SMBR, 3, NotSerialized) {
1698 Store (0x07, Local0)
1699 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1700 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1701 If (LEqual (Local0, Zero)) {
1707 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1709 If (LEqual (Arg0, 0x07)) {
1710 Store (0x48, HCNT) /* read byte */
1713 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1714 If (LEqual (Local1, Zero)) {
1715 If (LEqual (Arg0, 0x07)) {
1716 Store (DAT0, Local0)
1720 Store (Local1, Local0)
1726 /* DBGO("the value of SMBusData0 register ") */
1742 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1743 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1744 Return(Add(0, 2730))
1746 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1747 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1748 Return(Package() {\_TZ.TZ00.FAN0})
1751 Name(_HID, EISAID("PNP0C0B"))
1752 Name(_PR0, Package() {PFN0})
1755 PowerResource(PFN0,0,0) {
1761 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1764 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1768 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1769 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1770 Return (Add (THOT, KELV))
1772 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1773 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1774 Return (Add (TCRT, KELV))
1776 Method(_TMP,0) { /* return current temp of this zone */
1777 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1778 If (LGreater (Local0, 0x10)) {
1779 Store (Local0, Local1)
1782 Add (Local0, THOT, Local0)
1783 Return (Add (400, KELV))
1786 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1787 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1788 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1789 If (LGreater (Local0, 0x10)) {
1790 If (LGreater (Local0, Local1)) {
1791 Store (Local0, Local1)
1794 Multiply (Local1, 10, Local1)
1795 Return (Add (Local1, KELV))
1798 Add (Local0, THOT, Local0)
1799 Return (Add (400 , KELV))
1806 /* End of ASL file */