src/mainboard/asrock/939a785gmh/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RAMINIT_SYSINFO 1
  22 #define SET_FIDVID 1
  23 #define QRANK_DIMM_SUPPORT 1
  24 #if CONFIG_LOGICAL_CPUS==1
  25 #define SET_NB_CFG_54 1
  26 #endif
  27
  28 #define RC0 (6<<8)
  29 #define RC1 (7<<8)
  30
  31 #define DIMM0 0x50
  32 #define DIMM1 0x51
  33
  34 #define SMBUS_HUB 0x71
  35
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <device/pci_def.h>
  39 #include <arch/io.h>
  40 #include <device/pnp_def.h>
  41 #include <arch/romcc_io.h>
  42 #include <cpu/x86/lapic.h>
  43 #include <pc80/mc146818rtc.h>
  44 #include <console/console.h>
  45
  46 #include <cpu/amd/model_fxx_rev.h>
  47 #include "northbridge/amd/amdk8/raminit.h"
  48 #include "cpu/amd/model_fxx/apic_timer.c"
  49 #include "lib/delay.c"
  50
  51 #include "cpu/x86/lapic/boot_cpu.c"
  52 #include "northbridge/amd/amdk8/reset_test.c"
  53 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  54
  55 #if CONFIG_USBDEBUG
  56 #include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
  57 #include "pc80/usbdebug_serial.c"
  58 #endif
  59
  60 #include "cpu/x86/mtrr/earlymtrr.c"
  61 #include "cpu/x86/bist.h"
  62
  63 #include "northbridge/amd/amdk8/setup_resource_map.c"
  64
  65 #include "southbridge/amd/rs780/rs780_early_setup.c"
  66 #include "southbridge/amd/sb700/sb700_early_setup.c"
  67 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
  68
  69 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  70 #define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
  71 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
  72
  73 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  74 static void memreset(int controllers, const struct mem_controller *ctrl)
  75 {
  76 }
  77
  78 /* called in raminit_f.c */
  79 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  80 {
  81 }
  82
  83 /*called in raminit_f.c */
  84 static inline int spd_read_byte(u32 device, u32 address)
  85 {
  86         return smbus_read_byte(device, address);
  87 }
  88
  89 #include "northbridge/amd/amdk8/amdk8.h"
  90 #include "northbridge/amd/amdk8/incoherent_ht.c"
  91 #include "northbridge/amd/amdk8/raminit.c"
  92 #include "northbridge/amd/amdk8/coherent_ht.c"
  93 #include "lib/generic_sdram.c"
  94 #include "resourcemap.c"
  95
  96 #include "cpu/amd/dualcore/dualcore.c"
  97
  98
  99 #include "cpu/amd/car/post_cache_as_ram.c"
 100
 101 #include "cpu/amd/model_fxx/init_cpus.c"
 102
 103 #include "cpu/amd/model_fxx/fidvid.c"
 104
 105 #include "northbridge/amd/amdk8/early_ht.c"
 106
 107 static void sio_init(void)
 108 {
 109         u8 reg;
 110
 111         pnp_enter_ext_func_mode(GPIO2345_DEV);
 112         pnp_set_logical_device(GPIO2345_DEV);
 113
 114         /* Pin 119 ~ 120 GP21, GP20  */
 115         reg = pnp_read_config(GPIO2345_DEV, 0x29);
 116         pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
 117
 118         /* todo document this */
 119         pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
 120         pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
 121
 122
 123 //idx 30 e0 e1 e2 e3 e4 e5 e6  e7 e8 e9 f0 f1 f2 f3 f4  f5 f6 f7 fe
 124 //val 07 XX XX XX f6 0e 00 00  00 00 ff d6 96 00 40 d0  83 00 00 07
 125
 126 //GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
 127 //mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
 128 //DDR voltage 44 45 46
 129
 130         /* GPO20 - sideport voltage GPO23 - mgpuV */
 131         pnp_write_config(GPIO2345_DEV, 0x30, 0x07);     /* Enable GPIO 2,3,4. */
 132         pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6);     /* dir of GPIO2 11110110*/
 133         pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e);     /* data */
 134         pnp_write_config(GPIO2345_DEV, 0xe5, 0x00);     /* No inversion */
 135
 136         /* GPO30 GPO33 GPO35 */
 137         //GPO35 - loadline control 0 - enabled
 138         //GPIO30 - unknown
 139         //GPIO33 - unknown
 140         pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6);     /* dir of GPIO3 11010110*/
 141         pnp_write_config(GPIO2345_DEV, 0xf1, 0x96);     /* data */
 142         pnp_write_config(GPIO2345_DEV, 0xf2, 0x00);     /* No inversion */
 143
 144         /* GPO40 GPO41 GPO42 GPO43 PO45 */
 145         pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0);     /* dir of GPIO4 11010000 */
 146         pnp_write_config(GPIO2345_DEV, 0xf5, 0x83);     /* data */
 147         pnp_write_config(GPIO2345_DEV, 0xf6, 0x00);     /* No inversion */
 148
 149         pnp_write_config(GPIO2345_DEV, 0xf7, 0x00);     /* MFC */
 150         pnp_write_config(GPIO2345_DEV, 0xf8, 0x00);     /* MFC */
 151         pnp_write_config(GPIO2345_DEV, 0xfe, 0x07);     /* trig type */
 152         pnp_exit_ext_func_mode(GPIO2345_DEV);
 153 }
 154
 155 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 156 {
 157         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 158         int needs_reset = 0;
 159         u32 bsp_apicid = 0;
 160         msr_t msr;
 161         struct cpuid_result cpuid1;
 162         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 163
 164         if (!cpu_init_detectedx && boot_cpu()) {
 165                 /* Nothing special needs to be done to find bus 0 */
 166                 /* Allow the HT devices to be found */
 167                 enumerate_ht_chain();
 168
 169                 /* sb700_lpc_port80(); */
 170                 sb700_pci_port80();
 171         }
 172
 173         if (bist == 0) {
 174                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 175         }
 176
 177         enable_rs780_dev8();
 178         sb700_lpc_init();
 179
 180         sio_init();
 181         w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 182         uart_init();
 183
 184 #if CONFIG_USBDEBUG
 185         sb700_enable_usbdebug(0);
 186         early_usbdebug_init();
 187 #endif
 188
 189         console_init();
 190
 191         /* Halt if there was a built in self test failure */
 192         report_bist_failure(bist);
 193         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 194
 195         setup_939a785gmh_resource_map();
 196
 197         setup_coherent_ht_domain();
 198
 199 #if CONFIG_LOGICAL_CPUS==1
 200         /* It is said that we should start core1 after all core0 launched */
 201         wait_all_core0_started();
 202         start_other_cores();
 203 #endif
 204         wait_all_aps_started(bsp_apicid);
 205
 206         ht_setup_chains_x(sysinfo);
 207
 208         /* run _early_setup before soft-reset. */
 209         rs780_early_setup();
 210         sb700_early_setup();
 211
 212         /* Check to see if processor is capable of changing FIDVID  */
 213         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 214         cpuid1 = cpuid(0x80000007);
 215         if( (cpuid1.edx & 0x6) == 0x6 ) {
 216
 217                 /* Read FIDVID_STATUS */
 218                 msr=rdmsr(0xc0010042);
 219                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 220
 221                 enable_fid_change();
 222                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 223                 init_fidvid_bsp(bsp_apicid);
 224
 225                 /* show final fid and vid */
 226                 msr=rdmsr(0xc0010042);
 227                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 228
 229         } else {
 230                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 231         }
 232
 233         needs_reset = optimize_link_coherent_ht();
 234         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 235         rs780_htinit();
 236         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 237
 238         if (needs_reset) {
 239                 print_info("ht reset -\n");
 240                 soft_reset();
 241         }
 242
 243         allow_all_aps_stop(bsp_apicid);
 244
 245         /* It's the time to set ctrl now; */
 246         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 247                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 248         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 249         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 250
 251         rs780_before_pci_init();
 252         sb700_before_pci_init();
 253
 254         post_cache_as_ram();
 255 }
 256