2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #define RAMINIT_SYSINFO 1
23 #define QRANK_DIMM_SUPPORT 1
24 #if CONFIG_LOGICAL_CPUS==1
25 #define SET_NB_CFG_54 1
34 #define ICS951462_ADDRESS 0x69
35 #define SMBUS_HUB 0x71
39 #include <device/pci_def.h>
41 #include <device/pnp_def.h>
42 #include <arch/romcc_io.h>
43 #include <cpu/x86/lapic.h>
44 #include <pc80/mc146818rtc.h>
45 #include <console/console.h>
47 #include <cpu/amd/model_fxx_rev.h>
48 #include "northbridge/amd/amdk8/raminit.h"
49 #include "cpu/amd/model_fxx/apic_timer.c"
50 #include "lib/delay.c"
52 #include "cpu/x86/lapic/boot_cpu.c"
53 #include "northbridge/amd/amdk8/reset_test.c"
54 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
56 #include "cpu/x86/mtrr/earlymtrr.c"
57 #include "cpu/x86/bist.h"
59 #include "northbridge/amd/amdk8/setup_resource_map.c"
61 #include "southbridge/amd/rs780/rs780_early_setup.c"
62 #include "southbridge/amd/sb700/sb700_early_setup.c"
63 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
65 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
66 #define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
67 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
69 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
70 static void memreset(int controllers, const struct mem_controller *ctrl)
74 /* called in raminit_f.c */
75 static inline void activate_spd_rom(const struct mem_controller *ctrl)
79 /*called in raminit_f.c */
80 static inline int spd_read_byte(u32 device, u32 address)
82 return smbus_read_byte(device, address);
85 #include "northbridge/amd/amdk8/amdk8.h"
86 #include "northbridge/amd/amdk8/incoherent_ht.c"
87 #include "northbridge/amd/amdk8/raminit.c"
88 #include "northbridge/amd/amdk8/coherent_ht.c"
89 #include "lib/generic_sdram.c"
90 #include "resourcemap.c"
92 #include "cpu/amd/dualcore/dualcore.c"
95 #include "cpu/amd/car/post_cache_as_ram.c"
97 #include "cpu/amd/model_fxx/init_cpus.c"
99 #include "cpu/amd/model_fxx/fidvid.c"
101 #include "northbridge/amd/amdk8/early_ht.c"
103 static void sio_init(void)
107 pnp_enter_ext_func_mode(GPIO2345_DEV);
108 pnp_set_logical_device(GPIO2345_DEV);
110 /* Pin 119 ~ 120 GP21, GP20 */
111 reg = pnp_read_config(GPIO2345_DEV, 0x29);
112 pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
114 /* todo document this */
115 pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
116 pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
119 //idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe
120 //val 07 XX XX XX f6 0e 00 00 00 00 ff d6 96 00 40 d0 83 00 00 07
122 //GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
123 //mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
124 //DDR voltage 44 45 46
126 /* GPO20 - sideport voltage GPO23 - mgpuV */
127 pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */
128 pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/
129 pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
130 pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
132 /* GPO30 GPO33 GPO35 */
133 //GPO35 - loadline control 0 - enabled
136 pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/
137 pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */
138 pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */
140 /* GPO40 GPO41 GPO42 GPO43 PO45 */
141 pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */
142 pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */
143 pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */
145 pnp_write_config(GPIO2345_DEV, 0xf7, 0x00); /* MFC */
146 pnp_write_config(GPIO2345_DEV, 0xf8, 0x00); /* MFC */
147 pnp_write_config(GPIO2345_DEV, 0xfe, 0x07); /* trig type */
148 pnp_exit_ext_func_mode(GPIO2345_DEV);
151 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
153 static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
157 struct cpuid_result cpuid1;
158 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
160 if (!cpu_init_detectedx && boot_cpu()) {
161 /* Nothing special needs to be done to find bus 0 */
162 /* Allow the HT devices to be found */
163 enumerate_ht_chain();
165 /* sb700_lpc_port80(); */
170 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
177 w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
181 /* Halt if there was a built in self test failure */
182 report_bist_failure(bist);
183 printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
185 setup_939a785gmh_resource_map();
187 setup_coherent_ht_domain();
189 #if CONFIG_LOGICAL_CPUS==1
190 /* It is said that we should start core1 after all core0 launched */
191 wait_all_core0_started();
194 wait_all_aps_started(bsp_apicid);
196 ht_setup_chains_x(sysinfo);
198 /* run _early_setup before soft-reset. */
202 /* Check to see if processor is capable of changing FIDVID */
203 /* otherwise it will throw a GP# when reading FIDVID_STATUS */
204 cpuid1 = cpuid(0x80000007);
205 if( (cpuid1.edx & 0x6) == 0x6 ) {
207 /* Read FIDVID_STATUS */
208 msr=rdmsr(0xc0010042);
209 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
212 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
213 init_fidvid_bsp(bsp_apicid);
215 /* show final fid and vid */
216 msr=rdmsr(0xc0010042);
217 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
220 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
223 needs_reset = optimize_link_coherent_ht();
224 needs_reset |= optimize_link_incoherent_ht(sysinfo);
226 printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
229 print_info("ht reset -\n");
233 allow_all_aps_stop(bsp_apicid);
235 /* It's the time to set ctrl now; */
236 printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
237 sysinfo->nodes, sysinfo->ctrl, spd_addr);
238 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
239 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
241 rs780_before_pci_init();
242 sb700_before_pci_init();