src/mainboard/asrock/939a785gmh/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define SET_FIDVID 1
  22 #define QRANK_DIMM_SUPPORT 1
  23 #if CONFIG_LOGICAL_CPUS==1
  24 #define SET_NB_CFG_54 1
  25 #endif
  26
  27 #define RC0 (6<<8)
  28 #define RC1 (7<<8)
  29
  30 #define DIMM0 0x50
  31 #define DIMM1 0x51
  32
  33 #define SMBUS_HUB 0x71
  34
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <device/pci_def.h>
  38 #include <arch/io.h>
  39 #include <device/pnp_def.h>
  40 #include <arch/romcc_io.h>
  41 #include <cpu/x86/lapic.h>
  42 #include <pc80/mc146818rtc.h>
  43 #include <console/console.h>
  44
  45 #include <cpu/amd/model_fxx_rev.h>
  46 #include "northbridge/amd/amdk8/raminit.h"
  47 #include "cpu/amd/model_fxx/apic_timer.c"
  48 #include "lib/delay.c"
  49
  50 #include "cpu/x86/lapic/boot_cpu.c"
  51 #include "northbridge/amd/amdk8/reset_test.c"
  52 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  53 #include <usbdebug.h>
  54
  55 #include "cpu/x86/mtrr/earlymtrr.c"
  56 #include "cpu/x86/bist.h"
  57
  58 #include "northbridge/amd/amdk8/setup_resource_map.c"
  59
  60 #include "southbridge/amd/rs780/rs780_early_setup.c"
  61 #include "southbridge/amd/sb700/sb700_early_setup.c"
  62 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
  63
  64 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  65 #define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
  66 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
  67
  68 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  69 static void memreset(int controllers, const struct mem_controller *ctrl)
  70 {
  71 }
  72
  73 /* called in raminit_f.c */
  74 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  75 {
  76 }
  77
  78 /*called in raminit_f.c */
  79 static inline int spd_read_byte(u32 device, u32 address)
  80 {
  81         return smbus_read_byte(device, address);
  82 }
  83
  84 #include "northbridge/amd/amdk8/amdk8.h"
  85 #include "northbridge/amd/amdk8/incoherent_ht.c"
  86 #include "northbridge/amd/amdk8/raminit.c"
  87 #include "northbridge/amd/amdk8/coherent_ht.c"
  88 #include "lib/generic_sdram.c"
  89 #include "resourcemap.c"
  90
  91 #include "cpu/amd/dualcore/dualcore.c"
  92
  93
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98 #include "cpu/amd/model_fxx/fidvid.c"
  99
 100 #include "northbridge/amd/amdk8/early_ht.c"
 101
 102 static void sio_init(void)
 103 {
 104         u8 reg;
 105
 106         pnp_enter_ext_func_mode(GPIO2345_DEV);
 107         pnp_set_logical_device(GPIO2345_DEV);
 108
 109         /* Pin 119 ~ 120 GP21, GP20  */
 110         reg = pnp_read_config(GPIO2345_DEV, 0x29);
 111         pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
 112
 113         /* todo document this */
 114         pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
 115         pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
 116
 117
 118 //idx 30 e0 e1 e2 e3 e4 e5 e6  e7 e8 e9 f0 f1 f2 f3 f4  f5 f6 f7 fe
 119 //val 07 XX XX XX f6 0e 00 00  00 00 ff d6 96 00 40 d0  83 00 00 07
 120
 121 //GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
 122 //mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
 123 //DDR voltage 44 45 46
 124
 125         /* GPO20 - sideport voltage GPO23 - mgpuV */
 126         pnp_write_config(GPIO2345_DEV, 0x30, 0x07);     /* Enable GPIO 2,3,4. */
 127         pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6);     /* dir of GPIO2 11110110*/
 128         pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e);     /* data */
 129         pnp_write_config(GPIO2345_DEV, 0xe5, 0x00);     /* No inversion */
 130
 131         /* GPO30 GPO33 GPO35 */
 132         //GPO35 - loadline control 0 - enabled
 133         //GPIO30 - unknown
 134         //GPIO33 - unknown
 135         pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6);     /* dir of GPIO3 11010110*/
 136         pnp_write_config(GPIO2345_DEV, 0xf1, 0x96);     /* data */
 137         pnp_write_config(GPIO2345_DEV, 0xf2, 0x00);     /* No inversion */
 138
 139         /* GPO40 GPO41 GPO42 GPO43 PO45 */
 140         pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0);     /* dir of GPIO4 11010000 */
 141         pnp_write_config(GPIO2345_DEV, 0xf5, 0x83);     /* data */
 142         pnp_write_config(GPIO2345_DEV, 0xf6, 0x00);     /* No inversion */
 143
 144         pnp_write_config(GPIO2345_DEV, 0xf7, 0x00);     /* MFC */
 145         pnp_write_config(GPIO2345_DEV, 0xf8, 0x00);     /* MFC */
 146         pnp_write_config(GPIO2345_DEV, 0xfe, 0x07);     /* trig type */
 147         pnp_exit_ext_func_mode(GPIO2345_DEV);
 148 }
 149
 150 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 151 {
 152         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 153         int needs_reset = 0;
 154         u32 bsp_apicid = 0;
 155         msr_t msr;
 156         struct cpuid_result cpuid1;
 157         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 158
 159         if (!cpu_init_detectedx && boot_cpu()) {
 160                 /* Nothing special needs to be done to find bus 0 */
 161                 /* Allow the HT devices to be found */
 162                 enumerate_ht_chain();
 163
 164                 /* sb700_lpc_port80(); */
 165                 sb700_pci_port80();
 166         }
 167
 168         if (bist == 0) {
 169                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 170         }
 171
 172         enable_rs780_dev8();
 173         sb700_lpc_init();
 174
 175         sio_init();
 176         w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 177         uart_init();
 178
 179 #if CONFIG_USBDEBUG
 180         sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 181         early_usbdebug_init();
 182 #endif
 183
 184         console_init();
 185
 186         /* Halt if there was a built in self test failure */
 187         report_bist_failure(bist);
 188         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 189
 190         setup_939a785gmh_resource_map();
 191
 192         setup_coherent_ht_domain();
 193
 194 #if CONFIG_LOGICAL_CPUS==1
 195         /* It is said that we should start core1 after all core0 launched */
 196         wait_all_core0_started();
 197         start_other_cores();
 198 #endif
 199         wait_all_aps_started(bsp_apicid);
 200
 201         ht_setup_chains_x(sysinfo);
 202
 203         /* run _early_setup before soft-reset. */
 204         rs780_early_setup();
 205         sb700_early_setup();
 206
 207         /* Check to see if processor is capable of changing FIDVID  */
 208         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 209         cpuid1 = cpuid(0x80000007);
 210         if( (cpuid1.edx & 0x6) == 0x6 ) {
 211
 212                 /* Read FIDVID_STATUS */
 213                 msr=rdmsr(0xc0010042);
 214                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 215
 216                 enable_fid_change();
 217                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 218                 init_fidvid_bsp(bsp_apicid);
 219
 220                 /* show final fid and vid */
 221                 msr=rdmsr(0xc0010042);
 222                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 223
 224         } else {
 225                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 226         }
 227
 228         needs_reset = optimize_link_coherent_ht();
 229         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 230         rs780_htinit();
 231         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 232
 233         if (needs_reset) {
 234                 print_info("ht reset -\n");
 235                 soft_reset();
 236         }
 237
 238         allow_all_aps_stop(bsp_apicid);
 239
 240         /* It's the time to set ctrl now; */
 241         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 242                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 243         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 244         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 245
 246         rs780_before_pci_init();
 247         sb700_before_pci_init();
 248
 249         post_cache_as_ram();
 250 }
 251