2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
26 "939A785GM", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
40 Name(HPBA, 0xFED00000) /* Base address of HPET table */
42 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44 /* USB overcurrent mapping pins. */
56 /* Some global data */
57 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
58 Name(OSV, Ones) /* Assume nothing */
59 Name(PMOD, One) /* Assume APIC */
61 /* PIC IRQ mapping registers, C00h-C01h */
62 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
63 Field(PRQM, ByteAcc, NoLock, Preserve) {
65 PRQD, 0x00000008, /* Offset: 1h */
67 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
68 PINA, 0x00000008, /* Index 0 */
69 PINB, 0x00000008, /* Index 1 */
70 PINC, 0x00000008, /* Index 2 */
71 PIND, 0x00000008, /* Index 3 */
72 AINT, 0x00000008, /* Index 4 */
73 SINT, 0x00000008, /* Index 5 */
74 , 0x00000008, /* Index 6 */
75 AAUD, 0x00000008, /* Index 7 */
76 AMOD, 0x00000008, /* Index 8 */
77 PINE, 0x00000008, /* Index 9 */
78 PINF, 0x00000008, /* Index A */
79 PING, 0x00000008, /* Index B */
80 PINH, 0x00000008, /* Index C */
83 /* PCI Error control register */
84 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
85 Field(PERC, ByteAcc, NoLock, Preserve) {
92 /* Client Management index/data registers */
93 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
94 Field(CMT, ByteAcc, NoLock, Preserve) {
96 /* Client Management Data register */
104 /* GPM Port register */
105 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
106 Field(GPT, ByteAcc, NoLock, Preserve) {
117 /* Flash ROM program enable register */
118 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
119 Field(FRE, ByteAcc, NoLock, Preserve) {
124 /* PM2 index/data registers */
125 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
126 Field(PM2R, ByteAcc, NoLock, Preserve) {
131 /* Power Management I/O registers */
132 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
133 Field(PIOR, ByteAcc, NoLock, Preserve) {
137 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
138 Offset(0x00), /* MiscControl */
142 Offset(0x01), /* MiscStatus */
146 Offset(0x04), /* SmiWakeUpEventEnable3 */
149 Offset(0x07), /* SmiWakeUpEventStatus3 */
152 Offset(0x10), /* AcpiEnable */
155 Offset(0x1C), /* ProgramIoEnable */
162 Offset(0x1D), /* IOMonitorStatus */
169 Offset(0x20), /* AcpiPmEvtBlk */
171 Offset(0x36), /* GEvtLevelConfig */
175 Offset(0x37), /* GPMLevelConfig0 */
182 Offset(0x38), /* GPMLevelConfig1 */
189 Offset(0x3B), /* PMEStatus1 */
198 Offset(0x55), /* SoftPciRst */
206 /* Offset(0x61), */ /* Options_1 */
210 Offset(0x65), /* UsbPMControl */
213 Offset(0x68), /* MiscEnable68 */
217 Offset(0x92), /* GEVENTIN */
220 Offset(0x96), /* GPM98IN */
223 Offset(0x9A), /* EnhanceControl */
226 Offset(0xA8), /* PIO7654Enable */
231 Offset(0xA9), /* PIO7654Status */
239 * First word is PM1_Status, Second word is PM1_Enable
241 OperationRegion(P1EB, SystemIO, APEB, 0x04)
242 Field(P1EB, ByteAcc, NoLock, Preserve) {
267 /* PCIe Configuration Space for 16 busses */
268 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
269 Field(PCFG, ByteAcc, NoLock, Preserve) {
270 /* Byte offsets are computed using the following technique:
271 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
272 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
274 Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
276 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
287 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
290 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
292 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
294 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
296 P92E, 1, /* Port92 decode enable */
299 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
300 Field(SB5, AnyAcc, NoLock, Preserve){
302 Offset(0x120), /* Port 0 Task file status */
308 Offset(0x128), /* Port 0 Serial ATA status */
312 Offset(0x12C), /* Port 0 Serial ATA control */
314 Offset(0x130), /* Port 0 Serial ATA error */
319 offset(0x1A0), /* Port 1 Task file status */
325 Offset(0x1A8), /* Port 1 Serial ATA status */
329 Offset(0x1AC), /* Port 1 Serial ATA control */
331 Offset(0x1B0), /* Port 1 Serial ATA error */
336 Offset(0x220), /* Port 2 Task file status */
342 Offset(0x228), /* Port 2 Serial ATA status */
346 Offset(0x22C), /* Port 2 Serial ATA control */
348 Offset(0x230), /* Port 2 Serial ATA error */
353 Offset(0x2A0), /* Port 3 Task file status */
359 Offset(0x2A8), /* Port 3 Serial ATA status */
363 Offset(0x2AC), /* Port 3 Serial ATA control */
365 Offset(0x2B0), /* Port 3 Serial ATA error */
372 #include "acpi/routing.asl"
378 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
380 if(CondRefOf(\_OSI,Local1))
382 Store(1, OSTP) /* Assume some form of XP */
383 if (\_OSI("Windows 2006")) /* Vista */
388 If(WCMP(\_OS,"Linux")) {
389 Store(3, OSTP) /* Linux */
391 Store(4, OSTP) /* Gotta be WinCE */
397 Method(_PIC, 0x01, NotSerialized)
405 Method(CIRQ, 0x00, NotSerialized){
416 Name(IRQB, ResourceTemplate(){
417 IRQ(Level,ActiveLow,Shared){15}
420 Name(IRQP, ResourceTemplate(){
421 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
424 Name(PITF, ResourceTemplate(){
425 IRQ(Level,ActiveLow,Exclusive){9}
429 Name(_HID, EISAID("PNP0C0F"))
434 Return(0x0B) /* sata is invisible */
436 Return(0x09) /* sata is disabled */
438 } /* End Method(_SB.INTA._STA) */
441 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
443 } /* End Method(_SB.INTA._DIS) */
446 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
448 } /* Method(_SB.INTA._PRS) */
451 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
452 CreateWordField(IRQB, 0x1, IRQN)
453 ShiftLeft(1, PINA, IRQN)
455 } /* Method(_SB.INTA._CRS) */
458 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
459 CreateWordField(ARG0, 1, IRQM)
461 /* Use lowest available IRQ */
462 FindSetRightBit(IRQM, Local0)
467 } /* End Method(_SB.INTA._SRS) */
468 } /* End Device(INTA) */
471 Name(_HID, EISAID("PNP0C0F"))
476 Return(0x0B) /* sata is invisible */
478 Return(0x09) /* sata is disabled */
480 } /* End Method(_SB.INTB._STA) */
483 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
485 } /* End Method(_SB.INTB._DIS) */
488 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
490 } /* Method(_SB.INTB._PRS) */
493 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
494 CreateWordField(IRQB, 0x1, IRQN)
495 ShiftLeft(1, PINB, IRQN)
497 } /* Method(_SB.INTB._CRS) */
500 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
501 CreateWordField(ARG0, 1, IRQM)
503 /* Use lowest available IRQ */
504 FindSetRightBit(IRQM, Local0)
509 } /* End Method(_SB.INTB._SRS) */
510 } /* End Device(INTB) */
513 Name(_HID, EISAID("PNP0C0F"))
518 Return(0x0B) /* sata is invisible */
520 Return(0x09) /* sata is disabled */
522 } /* End Method(_SB.INTC._STA) */
525 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
527 } /* End Method(_SB.INTC._DIS) */
530 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
532 } /* Method(_SB.INTC._PRS) */
535 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
536 CreateWordField(IRQB, 0x1, IRQN)
537 ShiftLeft(1, PINC, IRQN)
539 } /* Method(_SB.INTC._CRS) */
542 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
543 CreateWordField(ARG0, 1, IRQM)
545 /* Use lowest available IRQ */
546 FindSetRightBit(IRQM, Local0)
551 } /* End Method(_SB.INTC._SRS) */
552 } /* End Device(INTC) */
555 Name(_HID, EISAID("PNP0C0F"))
560 Return(0x0B) /* sata is invisible */
562 Return(0x09) /* sata is disabled */
564 } /* End Method(_SB.INTD._STA) */
567 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
569 } /* End Method(_SB.INTD._DIS) */
572 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
574 } /* Method(_SB.INTD._PRS) */
577 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
578 CreateWordField(IRQB, 0x1, IRQN)
579 ShiftLeft(1, PIND, IRQN)
581 } /* Method(_SB.INTD._CRS) */
584 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
585 CreateWordField(ARG0, 1, IRQM)
587 /* Use lowest available IRQ */
588 FindSetRightBit(IRQM, Local0)
593 } /* End Method(_SB.INTD._SRS) */
594 } /* End Device(INTD) */
597 Name(_HID, EISAID("PNP0C0F"))
602 Return(0x0B) /* sata is invisible */
604 Return(0x09) /* sata is disabled */
606 } /* End Method(_SB.INTE._STA) */
609 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
611 } /* End Method(_SB.INTE._DIS) */
614 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
616 } /* Method(_SB.INTE._PRS) */
619 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
620 CreateWordField(IRQB, 0x1, IRQN)
621 ShiftLeft(1, PINE, IRQN)
623 } /* Method(_SB.INTE._CRS) */
626 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
627 CreateWordField(ARG0, 1, IRQM)
629 /* Use lowest available IRQ */
630 FindSetRightBit(IRQM, Local0)
635 } /* End Method(_SB.INTE._SRS) */
636 } /* End Device(INTE) */
639 Name(_HID, EISAID("PNP0C0F"))
644 Return(0x0B) /* sata is invisible */
646 Return(0x09) /* sata is disabled */
648 } /* End Method(_SB.INTF._STA) */
651 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
653 } /* End Method(_SB.INTF._DIS) */
656 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
658 } /* Method(_SB.INTF._PRS) */
661 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
662 CreateWordField(IRQB, 0x1, IRQN)
663 ShiftLeft(1, PINF, IRQN)
665 } /* Method(_SB.INTF._CRS) */
668 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
669 CreateWordField(ARG0, 1, IRQM)
671 /* Use lowest available IRQ */
672 FindSetRightBit(IRQM, Local0)
677 } /* End Method(_SB.INTF._SRS) */
678 } /* End Device(INTF) */
681 Name(_HID, EISAID("PNP0C0F"))
686 Return(0x0B) /* sata is invisible */
688 Return(0x09) /* sata is disabled */
690 } /* End Method(_SB.INTG._STA) */
693 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
695 } /* End Method(_SB.INTG._DIS) */
698 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
700 } /* Method(_SB.INTG._CRS) */
703 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
704 CreateWordField(IRQB, 0x1, IRQN)
705 ShiftLeft(1, PING, IRQN)
707 } /* Method(_SB.INTG._CRS) */
710 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
711 CreateWordField(ARG0, 1, IRQM)
713 /* Use lowest available IRQ */
714 FindSetRightBit(IRQM, Local0)
719 } /* End Method(_SB.INTG._SRS) */
720 } /* End Device(INTG) */
723 Name(_HID, EISAID("PNP0C0F"))
728 Return(0x0B) /* sata is invisible */
730 Return(0x09) /* sata is disabled */
732 } /* End Method(_SB.INTH._STA) */
735 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
737 } /* End Method(_SB.INTH._DIS) */
740 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
742 } /* Method(_SB.INTH._CRS) */
745 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
746 CreateWordField(IRQB, 0x1, IRQN)
747 ShiftLeft(1, PINH, IRQN)
749 } /* Method(_SB.INTH._CRS) */
752 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
753 CreateWordField(ARG0, 1, IRQM)
755 /* Use lowest available IRQ */
756 FindSetRightBit(IRQM, Local0)
761 } /* End Method(_SB.INTH._SRS) */
762 } /* End Device(INTH) */
764 } /* End Scope(_SB) */
767 /* Supported sleep states: */
768 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
770 If (LAnd(SSFG, 0x01)) {
771 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
773 If (LAnd(SSFG, 0x02)) {
774 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
776 If (LAnd(SSFG, 0x04)) {
777 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
779 If (LAnd(SSFG, 0x08)) {
780 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
783 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
785 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
786 Name(CSMS, 0) /* Current System State */
788 /* Wake status package */
789 Name(WKST,Package(){Zero, Zero})
792 * \_PTS - Prepare to Sleep method
795 * Arg0=The value of the sleeping state S1=1, S2=2, etc
800 * The _PTS control method is executed at the beginning of the sleep process
801 * for S1-S5. The sleeping value is passed to the _PTS control method. This
802 * control method may be executed a relatively long time before entering the
803 * sleep state and the OS may abort the operation without notification to
804 * the ACPI driver. This method cannot modify the configuration or power
805 * state of any device in the system.
808 /* DBGO("\\_PTS\n") */
809 /* DBGO("From S0 to S") */
813 /* Don't allow PCIRST# to reset USB */
818 /* Clear sleep SMI status flag and enable sleep SMI trap. */
822 /* On older chips, clear PciExpWakeDisEn */
823 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
828 /* Clear wake status structure. */
829 Store(0, Index(WKST,0))
830 Store(0, Index(WKST,1))
831 \_SB.PCI0.SIOS (Arg0)
832 } /* End Method(\_PTS) */
835 * The following method results in a "not a valid reserved NameSeg"
836 * warning so I have commented it out for the duration. It isn't
837 * used, so it could be removed.
840 * \_GTS OEM Going To Sleep method
843 * Arg0=The value of the sleeping state S1=1, S2=2
850 * DBGO("From S0 to S")
857 * \_BFS OEM Back From Sleep method
860 * Arg0=The value of the sleeping state S1=1, S2=2
866 /* DBGO("\\_BFS\n") */
869 /* DBGO(" to S0\n") */
873 * \_WAK System Wake method
876 * Arg0=The value of the sleeping state S1=1, S2=2
879 * Return package of 2 DWords
881 * 0x00000000 wake succeeded
882 * 0x00000001 Wake was signaled but failed due to lack of power
883 * 0x00000002 Wake was signaled but failed due to thermal condition
884 * Dword 2 - Power Supply state
885 * if non-zero the effective S-state the power supply entered
888 /* DBGO("\\_WAK\n") */
891 /* DBGO(" to S0\n") */
896 /* Restore PCIRST# so it resets USB */
901 /* Arbitrarily clear PciExpWakeStatus */
904 /* if(DeRefOf(Index(WKST,0))) {
905 * Store(0, Index(WKST,1))
907 * Store(Arg0, Index(WKST,1))
910 \_SB.PCI0.SIOW (Arg0)
912 } /* End Method(\_WAK) */
914 Scope(\_GPE) { /* Start Scope GPE */
915 /* General event 0 */
917 * DBGO("\\_GPE\\_L00\n")
921 /* General event 1 */
923 * DBGO("\\_GPE\\_L00\n")
927 /* General event 2 */
929 * DBGO("\\_GPE\\_L00\n")
933 /* General event 3 */
935 /* DBGO("\\_GPE\\_L00\n") */
936 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
939 /* General event 4 */
941 * DBGO("\\_GPE\\_L00\n")
945 /* General event 5 */
947 * DBGO("\\_GPE\\_L00\n")
951 /* General event 6 - Used for GPM6, moved to USB.asl */
953 * DBGO("\\_GPE\\_L00\n")
957 /* General event 7 - Used for GPM7, moved to USB.asl */
959 * DBGO("\\_GPE\\_L07\n")
963 /* Legacy PM event */
965 /* DBGO("\\_GPE\\_L08\n") */
968 /* Temp warning (TWarn) event */
970 /* DBGO("\\_GPE\\_L09\n") */
971 Notify (\_TZ.TZ00, 0x80)
976 * DBGO("\\_GPE\\_L0A\n")
980 /* USB controller PME# */
982 /* DBGO("\\_GPE\\_L0B\n") */
983 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
984 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
985 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
986 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
987 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
988 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
989 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
992 /* AC97 controller PME# */
994 * DBGO("\\_GPE\\_L0C\n")
998 /* OtherTherm PME# */
1000 * DBGO("\\_GPE\\_L0D\n")
1004 /* GPM9 SCI event - Moved to USB.asl */
1006 * DBGO("\\_GPE\\_L0E\n")
1010 /* PCIe HotPlug event */
1012 * DBGO("\\_GPE\\_L0F\n")
1016 /* ExtEvent0 SCI event */
1018 /* DBGO("\\_GPE\\_L10\n") */
1022 /* ExtEvent1 SCI event */
1024 /* DBGO("\\_GPE\\_L11\n") */
1027 /* PCIe PME# event */
1029 * DBGO("\\_GPE\\_L12\n")
1033 /* GPM0 SCI event - Moved to USB.asl */
1035 * DBGO("\\_GPE\\_L13\n")
1039 /* GPM1 SCI event - Moved to USB.asl */
1041 * DBGO("\\_GPE\\_L14\n")
1045 /* GPM2 SCI event - Moved to USB.asl */
1047 * DBGO("\\_GPE\\_L15\n")
1051 /* GPM3 SCI event - Moved to USB.asl */
1053 * DBGO("\\_GPE\\_L16\n")
1057 /* GPM8 SCI event - Moved to USB.asl */
1059 * DBGO("\\_GPE\\_L17\n")
1063 /* GPIO0 or GEvent8 event */
1065 /* DBGO("\\_GPE\\_L18\n") */
1066 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1067 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1070 /* GPM4 SCI event - Moved to USB.asl */
1072 * DBGO("\\_GPE\\_L19\n")
1076 /* GPM5 SCI event - Moved to USB.asl */
1078 * DBGO("\\_GPE\\_L1A\n")
1082 /* Azalia SCI event */
1084 /* DBGO("\\_GPE\\_L1B\n") */
1085 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1086 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1089 /* GPM6 SCI event - Reassigned to _L06 */
1091 * DBGO("\\_GPE\\_L1C\n")
1095 /* GPM7 SCI event - Reassigned to _L07 */
1097 * DBGO("\\_GPE\\_L1D\n")
1101 /* GPIO2 or GPIO66 SCI event */
1103 * DBGO("\\_GPE\\_L1E\n")
1107 /* SATA SCI event - Moved to sata.asl */
1109 * DBGO("\\_GPE\\_L1F\n")
1113 } /* End Scope GPE */
1115 #include "acpi/usb.asl"
1118 Scope(\_SB) { /* Start \_SB scope */
1119 #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1122 /* Note: Only need HID on Primary Bus */
1125 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1126 Name(_HID, EISAID("PNP0A03"))
1127 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1128 Method(_BBN, 0) { /* Bus number = 0 */
1132 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1133 Return(0x0B) /* Status is visible */
1137 If(PMOD){ Return(APR0) } /* APIC mode */
1138 Return (PR0) /* PIC Mode */
1141 /* Describe the Northbridge devices */
1143 Name(_ADR, 0x00000000)
1146 /* The internal GFX bridge */
1148 Name(_ADR, 0x00010000)
1149 Name(_PRW, Package() {0x18, 4})
1155 /* The external GFX bridge */
1157 Name(_ADR, 0x00020000)
1158 Name(_PRW, Package() {0x18, 4})
1160 If(PMOD){ Return(APS2) } /* APIC mode */
1161 Return (PS2) /* PIC Mode */
1167 Name(_ADR, 0x00090000)
1168 Name(_PRW, Package() {0x18, 4})
1170 If(PMOD){ Return(APS9) } /* APIC mode */
1171 Return (PS9) /* PIC Mode */
1177 Name(_ADR, 0x000A0000)
1178 Name(_PRW, Package() {0x18, 4})
1180 If(PMOD){ Return(APSa) } /* APIC mode */
1181 Return (PSa) /* PIC Mode */
1186 /* PCI slot 1, 2, 3 */
1188 Name(_ADR, 0x00140004)
1189 Name(_PRW, Package() {0x18, 4})
1196 /* Describe the Southbridge devices */
1198 Name(_ADR, 0x00110000)
1199 #include "acpi/sata.asl"
1203 Name(_ADR, 0x00130000)
1204 Name(_PRW, Package() {0x0B, 3})
1208 Name(_ADR, 0x00130001)
1209 Name(_PRW, Package() {0x0B, 3})
1213 Name(_ADR, 0x00130002)
1214 Name(_PRW, Package() {0x0B, 3})
1218 Name(_ADR, 0x00130003)
1219 Name(_PRW, Package() {0x0B, 3})
1223 Name(_ADR, 0x00130004)
1224 Name(_PRW, Package() {0x0B, 3})
1228 Name(_ADR, 0x00130005)
1229 Name(_PRW, Package() {0x0B, 3})
1233 Name(_ADR, 0x00140000)
1236 /* Primary (and only) IDE channel */
1238 Name(_ADR, 0x00140001)
1239 #include "acpi/ide.asl"
1243 Name(_ADR, 0x00140002)
1244 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1245 Field(AZPD, AnyAcc, NoLock, Preserve) {
1269 If(LEqual(OSTP,3)){ /* If we are running Linux */
1278 Name(_ADR, 0x00140003)
1280 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1281 } */ /* End Method(_SB.SBRDG._INI) */
1283 /* Real Time Clock Device */
1285 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1286 Name(_CRS, ResourceTemplate() {
1288 IO(Decode16,0x0070, 0x0070, 0, 2)
1289 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1291 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1293 Device(TMR) { /* Timer */
1294 Name(_HID,EISAID("PNP0100")) /* System Timer */
1295 Name(_CRS, ResourceTemplate() {
1297 IO(Decode16, 0x0040, 0x0040, 0, 4)
1298 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1300 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1302 Device(SPKR) { /* Speaker */
1303 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1304 Name(_CRS, ResourceTemplate() {
1305 IO(Decode16, 0x0061, 0x0061, 0, 1)
1307 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1310 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1311 Name(_CRS, ResourceTemplate() {
1313 IO(Decode16,0x0020, 0x0020, 0, 2)
1314 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1315 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1316 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1318 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1320 Device(MAD) { /* 8257 DMA */
1321 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1322 Name(_CRS, ResourceTemplate() {
1323 DMA(Compatibility,BusMaster,Transfer8){4}
1324 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1325 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1326 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1327 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1328 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1329 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1330 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1331 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1334 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1335 Name(_CRS, ResourceTemplate() {
1336 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1339 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1342 Name(_HID,EISAID("PNP0103"))
1343 Name(CRS,ResourceTemplate() {
1344 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1347 Return(0x0F) /* sata is visible */
1350 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1354 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1358 Name(_ADR, 0x00140004)
1359 } /* end HostPciBr */
1362 Name(_ADR, 0x00140005)
1363 } /* end Ac97audio */
1366 Name(_ADR, 0x00140006)
1367 } /* end Ac97modem */
1369 /* ITE8718 Support */
1370 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1371 Field (IOID, ByteAcc, NoLock, Preserve)
1373 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1376 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1379 LDN, 8, /* Logical Device Number */
1381 CID1, 8, /* Chip ID Byte 1, 0x87 */
1382 CID2, 8, /* Chip ID Byte 2, 0x12 */
1384 ACTR, 8, /* Function activate */
1386 APC0, 8, /* APC/PME Event Enable Register */
1387 APC1, 8, /* APC/PME Status Register */
1388 APC2, 8, /* APC/PME Control Register 1 */
1389 APC3, 8, /* Environment Controller Special Configuration Register */
1390 APC4, 8 /* APC/PME Control Register 2 */
1393 /* Enter the 8718 MB PnP Mode */
1399 Store(0x55, SIOI) /* 8718 magic number */
1401 /* Exit the 8718 MB PnP Mode */
1408 * Keyboard PME is routed to SB600 Gevent3. We can wake
1409 * up the system by pressing the key.
1413 /* We only enable KBD PME for S5. */
1414 If (LLess (Arg0, 0x05))
1417 /* DBGO("8718F\n") */
1420 Store (One, ACTR) /* Enable EC */
1424 */ /* falling edge. which mode? Not sure. */
1427 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1429 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1438 Store (Zero, APC0) /* disable keyboard PME */
1440 Store (0xFF, APC1) /* clear keyboard PME status */
1444 Name(CRES, ResourceTemplate() {
1445 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1447 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1448 0x0000, /* address granularity */
1449 0x0000, /* range minimum */
1450 0x0CF7, /* range maximum */
1451 0x0000, /* translation */
1455 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1456 0x0000, /* address granularity */
1457 0x0D00, /* range minimum */
1458 0xFFFF, /* range maximum */
1459 0x0000, /* translation */
1463 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1464 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1465 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1466 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1468 /* DRAM Memory from 1MB to TopMem */
1469 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1471 /* BIOS space just below 4GB */
1473 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1474 0x00, /* Granularity */
1475 0x00000000, /* Min */
1476 0x00000000, /* Max */
1477 0x00000000, /* Translation */
1478 0x00000001, /* Max-Min, RLEN */
1483 /* DRAM memory from 4GB to TopMem2 */
1484 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1485 0x00000000, /* Granularity */
1486 0x00000000, /* Min */
1487 0x00000000, /* Max */
1488 0x00000000, /* Translation */
1489 0x00000001, /* Max-Min, RLEN */
1494 /* BIOS space just below 16EB */
1495 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1496 0x00000000, /* Granularity */
1497 0x00000000, /* Min */
1498 0x00000000, /* Max */
1499 0x00000000, /* Translation */
1500 0x00000001, /* Max-Min, RLEN */
1505 }) /* End Name(_SB.PCI0.CRES) */
1508 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1510 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1511 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1512 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1513 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1514 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1515 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1517 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1518 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1519 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1520 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1522 If(LGreater(LOMH, 0xC0000)){
1523 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1524 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1527 /* Set size of memory from 1MB to TopMem */
1528 Subtract(TOM1, 0x100000, DMLL)
1531 * If(LNotEqual(TOM2, 0x00000000)){
1532 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1533 * ShiftLeft(TOM2, 20, Local0)
1534 * Subtract(Local0, 0x100000000, DMHL)
1538 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1539 If(LEqual(TOM2, 0x00000000)){
1540 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1543 Else { /* Otherwise, put the BIOS just below 16EB */
1544 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1548 Return(CRES) /* note to change the Name buffer */
1549 } /* end of Method(_SB.PCI0._CRS) */
1553 * FIRST METHOD CALLED UPON BOOT
1555 * 1. If debugging, print current OS and ACPI interpreter.
1556 * 2. Get PCI Interrupt routing from ACPI VSM, this
1557 * value is based on user choice in BIOS setup.
1560 /* DBGO("\\_SB\\_INI\n") */
1561 /* DBGO(" DSDT.ASL code from ") */
1562 /* DBGO(__DATE__) */
1564 /* DBGO(__TIME__) */
1565 /* DBGO("\n Sleep states supported: ") */
1567 /* DBGO(" \\_OS=") */
1569 /* DBGO("\n \\_REV=") */
1573 /* Determine the OS we're running on */
1576 /* On older chips, clear PciExpWakeDisEn */
1577 /*if (LLessEqual(\SBRI, 0x13)) {
1581 } /* End Method(_SB._INI) */
1582 } /* End Device(PCI0) */
1584 Device(PWRB) { /* Start Power button device */
1585 Name(_HID, EISAID("PNP0C0C"))
1587 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1588 Name(_STA, 0x0B) /* sata is invisible */
1590 } /* End \_SB scope */
1594 /* DBGO("\\_SI\\_SST\n") */
1595 /* DBGO(" New Indicator state: ") */
1599 } /* End Scope SI */
1603 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1604 Field (SMB0, ByteAcc, NoLock, Preserve) {
1605 HSTS, 8, /* SMBUS status */
1606 SSTS, 8, /* SMBUS slave status */
1607 HCNT, 8, /* SMBUS control */
1608 HCMD, 8, /* SMBUS host cmd */
1609 HADD, 8, /* SMBUS address */
1610 DAT0, 8, /* SMBUS data0 */
1611 DAT1, 8, /* SMBUS data1 */
1612 BLKD, 8, /* SMBUS block data */
1613 SCNT, 8, /* SMBUS slave control */
1614 SCMD, 8, /* SMBUS shaow cmd */
1615 SEVT, 8, /* SMBUS slave event */
1616 SDAT, 8 /* SMBUS slave data */
1619 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1621 Store (0xFA, Local0)
1622 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1630 Method (SWTC, 1, NotSerialized) {
1631 Store (Arg0, Local0)
1632 Store (0x07, Local2)
1634 While (LEqual (Local1, One)) {
1635 Store (And (HSTS, 0x1E), Local3)
1636 If (LNotEqual (Local3, Zero)) { /* read sucess */
1637 If (LEqual (Local3, 0x02)) {
1638 Store (Zero, Local2)
1641 Store (Zero, Local1)
1644 If (LLess (Local0, 0x0A)) { /* read failure */
1645 Store (0x10, Local2)
1646 Store (Zero, Local1)
1649 Sleep (0x0A) /* 10 ms, try again */
1650 Subtract (Local0, 0x0A, Local0)
1658 Method (SMBR, 3, NotSerialized) {
1659 Store (0x07, Local0)
1660 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1661 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1662 If (LEqual (Local0, Zero)) {
1668 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1670 If (LEqual (Arg0, 0x07)) {
1671 Store (0x48, HCNT) /* read byte */
1674 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1675 If (LEqual (Local1, Zero)) {
1676 If (LEqual (Arg0, 0x07)) {
1677 Store (DAT0, Local0)
1681 Store (Local1, Local0)
1687 /* DBGO("the value of SMBusData0 register ") */
1703 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1704 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1705 Return(Add(0, 2730))
1707 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1708 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1709 Return(Package() {\_TZ.TZ00.FAN0})
1712 Name(_HID, EISAID("PNP0C0B"))
1713 Name(_PR0, Package() {PFN0})
1716 PowerResource(PFN0,0,0) {
1722 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1725 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1729 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1730 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1731 Return (Add (THOT, KELV))
1733 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1734 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1735 Return (Add (TCRT, KELV))
1737 Method(_TMP,0) { /* return current temp of this zone */
1738 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1739 If (LGreater (Local0, 0x10)) {
1740 Store (Local0, Local1)
1743 Add (Local0, THOT, Local0)
1744 Return (Add (400, KELV))
1747 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1748 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1749 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1750 If (LGreater (Local0, 0x10)) {
1751 If (LGreater (Local0, Local1)) {
1752 Store (Local0, Local1)
1755 Multiply (Local1, 10, Local1)
1756 Return (Add (Local1, KELV))
1759 Add (Local0, THOT, Local0)
1760 Return (Add (400 , KELV))
1766 /* End of ASL file */