2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
26 "939A785GM", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
31 #include "northbridge/amd/amdk8/util.asl"
33 Name(HPBA, 0xFED00000) /* Base address of HPET table */
35 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
37 Name(PMOD, One) /* Assume APIC */
39 /* PIC IRQ mapping registers, C00h-C01h */
40 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
41 Field(PRQM, ByteAcc, NoLock, Preserve) {
43 PRQD, 0x00000008, /* Offset: 1h */
45 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
46 PINA, 0x00000008, /* Index 0 */
47 PINB, 0x00000008, /* Index 1 */
48 PINC, 0x00000008, /* Index 2 */
49 PIND, 0x00000008, /* Index 3 */
50 AINT, 0x00000008, /* Index 4 */
51 SINT, 0x00000008, /* Index 5 */
52 , 0x00000008, /* Index 6 */
53 AAUD, 0x00000008, /* Index 7 */
54 AMOD, 0x00000008, /* Index 8 */
55 PINE, 0x00000008, /* Index 9 */
56 PINF, 0x00000008, /* Index A */
57 PING, 0x00000008, /* Index B */
58 PINH, 0x00000008, /* Index C */
61 #include "acpi/routing.asl"
65 Method(_PIC, 0x01, NotSerialized)
74 Method(CIRQ, 0x00, NotSerialized){
85 Name(IRQB, ResourceTemplate(){
86 IRQ(Level,ActiveLow,Shared){15}
89 Name(IRQP, ResourceTemplate(){
90 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
93 Name(PITF, ResourceTemplate(){
94 IRQ(Level,ActiveLow,Exclusive){9}
98 Name(_HID, EISAID("PNP0C0F"))
103 Return(0x0B) /* sata is invisible */
105 Return(0x09) /* sata is disabled */
107 } /* End Method(_SB.INTA._STA) */
110 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
112 } /* End Method(_SB.INTA._DIS) */
115 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
117 } /* Method(_SB.INTA._PRS) */
120 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
121 CreateWordField(IRQB, 0x1, IRQN)
122 ShiftLeft(1, PINA, IRQN)
124 } /* Method(_SB.INTA._CRS) */
127 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
128 CreateWordField(ARG0, 1, IRQM)
130 /* Use lowest available IRQ */
131 FindSetRightBit(IRQM, Local0)
136 } /* End Method(_SB.INTA._SRS) */
137 } /* End Device(INTA) */
140 Name(_HID, EISAID("PNP0C0F"))
145 Return(0x0B) /* sata is invisible */
147 Return(0x09) /* sata is disabled */
149 } /* End Method(_SB.INTB._STA) */
152 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
154 } /* End Method(_SB.INTB._DIS) */
157 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
159 } /* Method(_SB.INTB._PRS) */
162 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
163 CreateWordField(IRQB, 0x1, IRQN)
164 ShiftLeft(1, PINB, IRQN)
166 } /* Method(_SB.INTB._CRS) */
169 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
170 CreateWordField(ARG0, 1, IRQM)
172 /* Use lowest available IRQ */
173 FindSetRightBit(IRQM, Local0)
178 } /* End Method(_SB.INTB._SRS) */
179 } /* End Device(INTB) */
182 Name(_HID, EISAID("PNP0C0F"))
187 Return(0x0B) /* sata is invisible */
189 Return(0x09) /* sata is disabled */
191 } /* End Method(_SB.INTC._STA) */
194 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
196 } /* End Method(_SB.INTC._DIS) */
199 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
201 } /* Method(_SB.INTC._PRS) */
204 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
205 CreateWordField(IRQB, 0x1, IRQN)
206 ShiftLeft(1, PINC, IRQN)
208 } /* Method(_SB.INTC._CRS) */
211 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
212 CreateWordField(ARG0, 1, IRQM)
214 /* Use lowest available IRQ */
215 FindSetRightBit(IRQM, Local0)
220 } /* End Method(_SB.INTC._SRS) */
221 } /* End Device(INTC) */
224 Name(_HID, EISAID("PNP0C0F"))
229 Return(0x0B) /* sata is invisible */
231 Return(0x09) /* sata is disabled */
233 } /* End Method(_SB.INTD._STA) */
236 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
238 } /* End Method(_SB.INTD._DIS) */
241 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
243 } /* Method(_SB.INTD._PRS) */
246 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
247 CreateWordField(IRQB, 0x1, IRQN)
248 ShiftLeft(1, PIND, IRQN)
250 } /* Method(_SB.INTD._CRS) */
253 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
254 CreateWordField(ARG0, 1, IRQM)
256 /* Use lowest available IRQ */
257 FindSetRightBit(IRQM, Local0)
262 } /* End Method(_SB.INTD._SRS) */
263 } /* End Device(INTD) */
266 Name(_HID, EISAID("PNP0C0F"))
271 Return(0x0B) /* sata is invisible */
273 Return(0x09) /* sata is disabled */
275 } /* End Method(_SB.INTE._STA) */
278 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
280 } /* End Method(_SB.INTE._DIS) */
283 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
285 } /* Method(_SB.INTE._PRS) */
288 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
289 CreateWordField(IRQB, 0x1, IRQN)
290 ShiftLeft(1, PINE, IRQN)
292 } /* Method(_SB.INTE._CRS) */
295 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
296 CreateWordField(ARG0, 1, IRQM)
298 /* Use lowest available IRQ */
299 FindSetRightBit(IRQM, Local0)
304 } /* End Method(_SB.INTE._SRS) */
305 } /* End Device(INTE) */
308 Name(_HID, EISAID("PNP0C0F"))
313 Return(0x0B) /* sata is invisible */
315 Return(0x09) /* sata is disabled */
317 } /* End Method(_SB.INTF._STA) */
320 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
322 } /* End Method(_SB.INTF._DIS) */
325 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
327 } /* Method(_SB.INTF._PRS) */
330 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
331 CreateWordField(IRQB, 0x1, IRQN)
332 ShiftLeft(1, PINF, IRQN)
334 } /* Method(_SB.INTF._CRS) */
337 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
338 CreateWordField(ARG0, 1, IRQM)
340 /* Use lowest available IRQ */
341 FindSetRightBit(IRQM, Local0)
346 } /* End Method(_SB.INTF._SRS) */
347 } /* End Device(INTF) */
350 Name(_HID, EISAID("PNP0C0F"))
355 Return(0x0B) /* sata is invisible */
357 Return(0x09) /* sata is disabled */
359 } /* End Method(_SB.INTG._STA) */
362 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
364 } /* End Method(_SB.INTG._DIS) */
367 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
369 } /* Method(_SB.INTG._CRS) */
372 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
373 CreateWordField(IRQB, 0x1, IRQN)
374 ShiftLeft(1, PING, IRQN)
376 } /* Method(_SB.INTG._CRS) */
379 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
380 CreateWordField(ARG0, 1, IRQM)
382 /* Use lowest available IRQ */
383 FindSetRightBit(IRQM, Local0)
388 } /* End Method(_SB.INTG._SRS) */
389 } /* End Device(INTG) */
392 Name(_HID, EISAID("PNP0C0F"))
397 Return(0x0B) /* sata is invisible */
399 Return(0x09) /* sata is disabled */
401 } /* End Method(_SB.INTH._STA) */
404 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
406 } /* End Method(_SB.INTH._DIS) */
409 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
411 } /* Method(_SB.INTH._CRS) */
414 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
415 CreateWordField(IRQB, 0x1, IRQN)
416 ShiftLeft(1, PINH, IRQN)
418 } /* Method(_SB.INTH._CRS) */
421 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
422 CreateWordField(ARG0, 1, IRQM)
424 /* Use lowest available IRQ */
425 FindSetRightBit(IRQM, Local0)
430 } /* End Method(_SB.INTH._SRS) */
431 } /* End Device(INTH) */
433 } /* End Scope(_SB) */
436 /* Supported sleep states: */
437 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
439 If (LAnd(SSFG, 0x01)) {
440 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
442 If (LAnd(SSFG, 0x02)) {
443 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
445 If (LAnd(SSFG, 0x04)) {
446 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
448 If (LAnd(SSFG, 0x08)) {
449 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
452 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
454 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
455 Name(CSMS, 0) /* Current System State */
457 /* Wake status package */
459 Name(WKST,Package(){Zero, Zero})
462 Scope(\_SB) { /* Start \_SB scope */
463 #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
466 /* Note: Only need HID on Primary Bus */
469 Name(_HID, EISAID("PNP0A03"))
470 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
471 Method(_BBN, 0) { /* Bus number = 0 */
475 /* DBGO("\\_SB\\PCI0\\_STA\n") */
476 Return(0x0B) /* Status is visible */
480 If(PMOD){ Return(APR0) } /* APIC mode */
481 Return (PR0) /* PIC Mode */
484 /* Describe the Northbridge devices */
486 Name(_ADR, 0x00000000)
489 /* The internal GFX bridge */
491 Name(_ADR, 0x00010000)
492 Name(_PRW, Package() {0x18, 4})
498 /* The external GFX bridge */
500 Name(_ADR, 0x00020000)
501 Name(_PRW, Package() {0x18, 4})
503 If(PMOD){ Return(APS2) } /* APIC mode */
504 Return (PS2) /* PIC Mode */
510 Name(_ADR, 0x00090000)
511 Name(_PRW, Package() {0x18, 4})
513 If(PMOD){ Return(APS9) } /* APIC mode */
514 Return (PS9) /* PIC Mode */
520 Name(_ADR, 0x000A0000)
521 Name(_PRW, Package() {0x18, 4})
523 If(PMOD){ Return(APSa) } /* APIC mode */
524 Return (PSa) /* PIC Mode */
529 /* PCI slot 1, 2, 3 */
531 Name(_ADR, 0x00140004)
532 Name(_PRW, Package() {0x18, 4})
540 Name(_ADR, 0x00140003)
542 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
543 } */ /* End Method(_SB.SBRDG._INI) */
545 /* Real Time Clock Device */
547 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
548 Name(_CRS, ResourceTemplate() {
550 IO(Decode16,0x0070, 0x0070, 0, 2)
551 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
553 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
555 Device(TMR) { /* Timer */
556 Name(_HID,EISAID("PNP0100")) /* System Timer */
557 Name(_CRS, ResourceTemplate() {
559 IO(Decode16, 0x0040, 0x0040, 0, 4)
560 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
562 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
564 Device(SPKR) { /* Speaker */
565 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
566 Name(_CRS, ResourceTemplate() {
567 IO(Decode16, 0x0061, 0x0061, 0, 1)
569 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
572 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
573 Name(_CRS, ResourceTemplate() {
575 IO(Decode16,0x0020, 0x0020, 0, 2)
576 IO(Decode16,0x00A0, 0x00A0, 0, 2)
577 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
578 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
580 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
582 Device(MAD) { /* 8257 DMA */
583 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
584 Name(_CRS, ResourceTemplate() {
585 DMA(Compatibility,BusMaster,Transfer8){4}
586 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
587 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
588 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
589 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
590 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
591 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
592 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
593 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
596 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
597 Name(_CRS, ResourceTemplate() {
598 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
601 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
604 Name(_HID,EISAID("PNP0103"))
605 Name(CRS,ResourceTemplate() {
606 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
609 Return(0x0F) /* sata is visible */
612 CreateDwordField(CRS, ^HPT._BAS, HPBA)
616 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
628 Method (_CRS, 0, NotSerialized)
630 Name (BUF0, ResourceTemplate ()
633 0x0CF8, // Address Range Minimum
634 0x0CF8, // Address Range Maximum
635 0x01, // Address Alignment
636 0x08, // Address Length
638 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
639 0x0000, // Address Space Granularity
640 0x0000, // Address Range Minimum
641 0x0CF7, // Address Range Maximum
642 0x0000, // Address Translation Offset
643 0x0CF8, // Address Length
646 /* Methods bellow use SSDT to get actual MMIO regs
647 The IO ports are from 0xd00, optionally an VGA,
648 otherwise the info from MMIO is used.
650 Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
651 Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
652 Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
656 } /* End Device(PCI0) */
658 } /* End \_SB scope */
660 /* End of ASL file */