src/mainboard/artecgroup/dbe61/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/hlt.h>
   9 #include "pc80/serial.c"
  10 #include "arch/i386/lib/console.c"
  11 #include "ram/ramtest.c"
  12 //#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  13 #include "cpu/x86/bist.h"
  14 #include "cpu/x86/msr.h"
  15 #include <cpu/amd/lxdef.h>
  16
  17 //#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  18
  19 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
  20 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
  21
  22 static inline int spd_read_byte(unsigned device, unsigned address)
  23 {
  24         return smbus_read_byte(device, address);
  25 }
  26
  27 #include "northbridge/amd/lx/raminit.h"
  28
  29 static inline unsigned int fls(unsigned int x)
  30 {
  31         int r;
  32
  33         __asm__("bsfl %1,%0\n\t"
  34                 "jnz 1f\n\t"
  35                 "movl $32,%0\n"
  36                 "1:" : "=r" (r) : "g" (x));
  37         return r;
  38 }
  39
  40 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
  41 {
  42         /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
  43          *                      component Banks (byte 17) * module banks, side (byte 5) *
  44          *                      width in bits (byte 6,7)
  45          *                    = Density per side (byte 31) * number of sides (byte 5) */
  46         /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
  47         msr_t msr;
  48         unsigned char module_banks, val;
  49
  50         msr.hi = 0x10075012;
  51         msr.lo = 0x00000040;
  52
  53         wrmsr(MC_CF07_DATA, msr);               //GX3
  54
  55         /* timing and mode ... */
  56
  57         //msr = rdmsr(0x20000019);
  58
  59         /* per standard bios settings */
  60 /*
  61         msr.hi = 0x18000108;
  62         msr.lo =
  63                         (6<<28) |               // cas_lat
  64                         (10<<24)|               // ref2act
  65                         (7<<20)|                // act2pre
  66                         (3<<16)|                // pre2act
  67                         (3<<12)|                // act2cmd
  68                         (2<<8)|                 // act2act
  69                         (2<<6)|                 // dplwr
  70                         (2<<4)|                 // dplrd
  71                         (3);                    // dal
  72         * the msr value reported by quanta is very, very different.
  73          * we will go with that value for now.
  74          *
  75         //msr.lo = 0x286332a3;
  76 */
  77         //wrmsr(0x20000019, msr);       //GX3
  78
  79 }
  80
  81 #include "northbridge/amd/lx/raminit.c"
  82 #include "sdram/generic_sdram.c"
  83
  84 /* CPU and GLIU mult/div */
  85 #define PLLMSRhi 0x0000039C
  86 /* Hold Count - how long we will sit in reset */
  87 #define PLLMSRlo 0x00DE0000
  88
  89 #include "northbridge/amd/lx/pll_reset.c"
  90 #include "cpu/amd/model_lx/cpureginit.c"
  91 #include "cpu/amd/model_lx/syspreinit.c"
  92
  93 static void msr_init(void)
  94 {
  95         __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
  96         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
  97
  98         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
  99         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
 100 }
 101
 102
 103 static void main(unsigned long bist)
 104 {
 105         static const struct mem_controller memctrl [] = {
 106                 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
 107         };
 108
 109         SystemPreInit();                        //GX3 OK
 110
 111         msr_init();                                     //GX3 OK
 112
 113         cs5536_early_setup();           //GX3 OK
 114
 115         /* NOTE: must do this AFTER the early_setup!
 116          * it is counting on some early MSR setup
 117          * for cs5536
 118          */
 119         cs5536_setup_onchipuart();      //GX3 OK
 120
 121         uart_init();                            //GX3 OK
 122         console_init();                         //GX3 OK
 123
 124         pll_reset();                            //GX3 OK
 125
 126         cpuRegInit();                           //GX3 OK
 127
 128         print_err("done cpuRegInit\n");
 129
 130         sdram_initialize(1, memctrl);   //GX3 OK almost
 131
 132         /* Check all of memory */
 133         //ram_check(0x00000000, 640*1024);
 134 }