src/mainboard/arima/hdama/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10
  11 #include <cpu/amd/model_fxx_rev.h>
  12 #include "northbridge/amd/amdk8/incoherent_ht.c"
  13 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  22
  23 #include "cpu/x86/mtrr/earlymtrr.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #include "northbridge/amd/amdk8/setup_resource_map.c"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  29
  30 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  31
  32 /*
  33  * GPIO28 of 8111 will control H0_MEMRESET_L
  34  * GPIO29 of 8111 will control H1_MEMRESET_L
  35  */
  36 static void memreset_setup(void)
  37 {
  38         if (is_cpu_pre_c0()) {
  39                 /* Set the memreset low */
  40                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  41                 /* Ensure the BIOS has control of the memory lines */
  42                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  43         }
  44         else {
  45                 /* Ensure the CPU has controll of the memory lines */
  46                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  47         }
  48 }
  49
  50 static void memreset(int controllers, const struct mem_controller *ctrl)
  51 {
  52         if (is_cpu_pre_c0()) {
  53                 udelay(800);
  54                 /* Set memreset_high */
  55                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  56                 udelay(90);
  57         }
  58 }
  59
  60 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  61 {
  62         /* nothing to do */
  63 }
  64
  65 static inline int spd_read_byte(unsigned device, unsigned address)
  66 {
  67         return smbus_read_byte(device, address);
  68 }
  69
  70 #define QRANK_DIMM_SUPPORT 1
  71
  72 #include "northbridge/amd/amdk8/raminit.c"
  73 #include "northbridge/amd/amdk8/resourcemap.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76
  77 #if CONFIG_LOGICAL_CPUS==1
  78 #define SET_NB_CFG_54 1
  79 #endif
  80 #include "cpu/amd/dualcore/dualcore.c"
  81
  82 #define FIRST_CPU  1
  83 #define SECOND_CPU 1
  84 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  85
  86
  87
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91
  92 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  93 #include "northbridge/amd/amdk8/early_ht.c"
  94
  95 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  96 {
  97         static const uint16_t spd_addr [] = {
  98                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  99                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 100 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 101                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 102                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 103 #endif
 104         };
 105
 106         int needs_reset;
 107         unsigned bsp_apicid = 0;
 108         struct mem_controller ctrl[8];
 109         unsigned nodes;
 110
 111         if (!cpu_init_detectedx && boot_cpu()) {
 112                 /* Nothing special needs to be done to find bus 0 */
 113                 /* Allow the HT devices to be found */
 114
 115                 enumerate_ht_chain();
 116
 117                 amd8111_enable_rom();
 118         }
 119
 120         if (bist == 0) {
 121                 bsp_apicid = init_cpus(cpu_init_detectedx);
 122         }
 123
 124         pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 125         uart_init();
 126         console_init();
 127
 128         /* Halt if there was a built in self test failure */
 129         report_bist_failure(bist);
 130
 131         setup_default_resource_map();
 132
 133         needs_reset = setup_coherent_ht_domain();
 134
 135 #if CONFIG_LOGICAL_CPUS==1
 136         // It is said that we should start core1 after all core0 launched
 137         start_other_cores();
 138         wait_all_other_cores_started(bsp_apicid);
 139 #endif
 140         /* This is needed to be able to call udelay().  It could be moved to
 141          * memreset_setup, since udelay is called in memreset. */
 142         init_timer();
 143
 144         // automatically set that for you, but you might meet tight space
 145         needs_reset |= ht_setup_chains_x();
 146
 147         if (needs_reset) {
 148                 print_info("ht reset -\n");
 149                 soft_reset();
 150         }
 151
 152         allow_all_aps_stop(bsp_apicid);
 153
 154         nodes = get_nodes();
 155
 156         fill_mem_ctrl(nodes, ctrl, spd_addr);
 157
 158         enable_smbus();
 159
 160         memreset_setup();
 161
 162         sdram_initialize(nodes, ctrl);
 163
 164         post_cache_as_ram();
 165 }
 166