src/mainboard/arima/hdama/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "console/console.c"
  12 #include "lib/ramtest.c"
  13
  14 #include <cpu/amd/model_fxx_rev.h>
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  25
  26 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  32
  33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  34
  35 /*
  36  * GPIO28 of 8111 will control H0_MEMRESET_L
  37  * GPIO29 of 8111 will control H1_MEMRESET_L
  38  */
  39 static void memreset_setup(void)
  40 {
  41         if (is_cpu_pre_c0()) {
  42                 /* Set the memreset low */
  43                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  44                 /* Ensure the BIOS has control of the memory lines */
  45                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  46         }
  47         else {
  48                 /* Ensure the CPU has controll of the memory lines */
  49                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  50         }
  51 }
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl)
  54 {
  55         if (is_cpu_pre_c0()) {
  56                 udelay(800);
  57                 /* Set memreset_high */
  58                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  59                 udelay(90);
  60         }
  61 }
  62
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65         /* nothing to do */
  66 }
  67
  68 static inline int spd_read_byte(unsigned device, unsigned address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #define QRANK_DIMM_SUPPORT 1
  74
  75 #include "northbridge/amd/amdk8/raminit.c"
  76 #include "northbridge/amd/amdk8/resourcemap.c"
  77 #include "northbridge/amd/amdk8/coherent_ht.c"
  78 #include "lib/generic_sdram.c"
  79
  80 #if CONFIG_LOGICAL_CPUS==1
  81 #define SET_NB_CFG_54 1
  82 #endif
  83 #include "cpu/amd/dualcore/dualcore.c"
  84
  85 #define FIRST_CPU  1
  86 #define SECOND_CPU 1
  87 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  88
  89
  90
  91 #include "cpu/amd/car/post_cache_as_ram.c"
  92
  93 #include "cpu/amd/model_fxx/init_cpus.c"
  94
  95 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  96 #include "northbridge/amd/amdk8/early_ht.c"
  97
  98 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  99 {
 100         static const uint16_t spd_addr [] = {
 101                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 102                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 103 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 104                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 105                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 106 #endif
 107         };
 108
 109         int needs_reset;
 110         unsigned bsp_apicid = 0;
 111         struct mem_controller ctrl[8];
 112         unsigned nodes;
 113
 114         if (!cpu_init_detectedx && boot_cpu()) {
 115                 /* Nothing special needs to be done to find bus 0 */
 116                 /* Allow the HT devices to be found */
 117
 118                 enumerate_ht_chain();
 119
 120                 amd8111_enable_rom();
 121         }
 122
 123         if (bist == 0) {
 124                 bsp_apicid = init_cpus(cpu_init_detectedx);
 125         }
 126
 127         pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 128         uart_init();
 129         console_init();
 130
 131         /* Halt if there was a built in self test failure */
 132         report_bist_failure(bist);
 133
 134         setup_default_resource_map();
 135
 136         needs_reset = setup_coherent_ht_domain();
 137
 138 #if CONFIG_LOGICAL_CPUS==1
 139         // It is said that we should start core1 after all core0 launched
 140         start_other_cores();
 141         wait_all_other_cores_started(bsp_apicid);
 142 #endif
 143         /* This is needed to be able to call udelay().  It could be moved to
 144          * memreset_setup, since udelay is called in memreset. */
 145         init_timer();
 146
 147         // automatically set that for you, but you might meet tight space
 148         needs_reset |= ht_setup_chains_x();
 149
 150         if (needs_reset) {
 151                 print_info("ht reset -\n");
 152                 soft_reset();
 153         }
 154
 155         allow_all_aps_stop(bsp_apicid);
 156
 157         nodes = get_nodes();
 158
 159         fill_mem_ctrl(nodes, ctrl, spd_addr);
 160
 161         enable_smbus();
 162
 163         memreset_setup();
 164
 165         sdram_initialize(nodes, ctrl);
 166
 167         post_cache_as_ram();
 168 }
 169