1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/x86/lapic.h>
10 #define HT_INIT_CONTROL 0x6c
11 #define HTIC_BIOSR_Detect (1<<5)
13 /* If we assume a symmetric processor configuration we can
14 * get all of the information we need to write the processor
15 * entry from the bootstrap processor.
16 * Plus I don't think linux really even cares.
17 * Having the proper apicid's in the table so the non-bootstrap
18 * processors can be woken up should be enough. Linux-2.6.11 work-around.
20 static void smp_write_processors_inorder(struct mp_config_table *mc)
24 unsigned apic_version;
25 unsigned cpu_features;
26 unsigned cpu_feature_flags;
27 struct cpuid_result result;
30 boot_apic_id = lapicid();
31 apic_version = lapic_read(LAPIC_LVR) & 0xff;
33 cpu_features = result.eax;
34 cpu_feature_flags = result.edx;
35 /* order the output of the cpus to fix a bug in kernel 6 11 */
36 for(order_id = 0;order_id <256; order_id++) {
37 for(cpu = all_devices; cpu; cpu = cpu->next) {
38 unsigned long cpu_flag;
39 if ((cpu->path.type != DEVICE_PATH_APIC) ||
40 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
47 cpu_flag = MPC_CPU_ENABLED;
48 if (boot_apic_id == cpu->path.apic.apic_id) {
49 cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
51 if(cpu->path.apic.apic_id == order_id) {
52 smp_write_processor(mc,
53 cpu->path.apic.apic_id, apic_version,
54 cpu_flag, cpu_features, cpu_feature_flags);
61 static unsigned node_link_to_bus(unsigned node, unsigned link)
66 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
70 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
75 config_map = pci_read_config32(dev, reg);
76 if ((config_map & 3) != 3) {
79 dst_node = (config_map >> 4) & 7;
80 dst_link = (config_map >> 8) & 3;
81 bus_base = (config_map >> 16) & 0xff;
83 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
84 dst_node, dst_link, bus_base,
87 if ((dst_node == node) && (dst_link == link))
95 static unsigned max_apicid(void)
100 for(dev = all_devices; dev; dev = dev->next) {
101 if (dev->path.type != DEVICE_PATH_APIC)
103 if (dev->path.apic.apic_id > max) {
104 max = dev->path.apic.apic_id;
110 static void *smp_write_config_table(void *v)
112 static const char sig[4] = "PCMP";
113 static const char oem[8] = "COREBOOT";
114 static const char productid[12] = "HDAMA ";
115 struct mp_config_table *mc;
116 unsigned char bus_num;
117 unsigned char bus_isa;
118 unsigned char bus_chain_0;
119 unsigned char bus_8131_1;
120 unsigned char bus_8131_2;
121 unsigned char bus_8111_1;
122 unsigned apicid_base;
123 unsigned apicid_8111;
124 unsigned apicid_8131_1;
125 unsigned apicid_8131_2;
127 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
128 memset(mc, 0, sizeof(*mc));
130 memcpy(mc->mpc_signature, sig, sizeof(sig));
131 mc->mpc_length = sizeof(*mc); /* initially just the header */
133 mc->mpc_checksum = 0; /* not yet computed */
134 memcpy(mc->mpc_oem, oem, sizeof(oem));
135 memcpy(mc->mpc_productid, productid, sizeof(productid));
138 mc->mpc_entry_count = 0; /* No entries yet... */
139 mc->mpc_lapic = LAPIC_ADDR;
141 mc->mpe_checksum = 0;
144 smp_write_processors_inorder(mc);
146 apicid_base = max_apicid() + 1;
147 apicid_8111 = apicid_base;
148 apicid_8131_1 = apicid_base + 1;
149 apicid_8131_2 = apicid_base + 2;
154 bus_chain_0 = node_link_to_bus(0, 0);
155 if (bus_chain_0 == 0xff) {
156 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
161 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
163 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
164 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
168 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
174 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
176 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
180 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
185 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
187 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
191 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
197 /* define bus and isa numbers */
198 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
199 smp_write_bus(mc, bus_num, "PCI ");
201 smp_write_bus(mc, bus_isa, "ISA ");
203 /* IOAPIC handling */
204 smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
207 struct resource *res;
209 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1));
211 res = find_resource(dev, PCI_BASE_ADDRESS_0);
213 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
217 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,1));
219 res = find_resource(dev, PCI_BASE_ADDRESS_0);
221 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
226 /* ISA backward compatibility interrupts */
227 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
228 bus_isa, 0x00, apicid_8111, 0x00);
229 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
230 bus_isa, 0x01, apicid_8111, 0x01);
231 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
232 bus_isa, 0x00, apicid_8111, 0x02);
233 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
234 bus_isa, 0x03, apicid_8111, 0x03);
235 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
236 bus_isa, 0x04, apicid_8111, 0x04);
237 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
238 bus_isa, 0x05, apicid_8111, 0x05);
239 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
240 bus_isa, 0x06, apicid_8111, 0x06);
241 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
242 bus_isa, 0x07, apicid_8111, 0x07);
243 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
244 bus_isa, 0x08, apicid_8111, 0x08);
245 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
246 bus_isa, 0x09, apicid_8111, 0x09);
247 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
248 bus_isa, 0x0a, apicid_8111, 0x0a);
249 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
250 bus_isa, 0x0b, apicid_8111, 0x0b);
251 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
252 bus_isa, 0x0c, apicid_8111, 0x0c);
253 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
254 bus_isa, 0x0d, apicid_8111, 0x0d);
255 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
256 bus_isa, 0x0e, apicid_8111, 0x0e);
257 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
258 bus_isa, 0x0f, apicid_8111, 0x0f);
260 /* Standard local interrupt assignments */
261 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
262 bus_isa, 0x00, MP_APIC_ALL, 0x00);
263 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
264 bus_isa, 0x00, MP_APIC_ALL, 0x01);
266 /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
268 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, apicid_8111, 0x13);
269 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, apicid_8111, 0x13);
271 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x05<<2)|0, apicid_8111, 0x11);
274 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, apicid_8111, 0x11);
275 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, apicid_8111, 0x12);
276 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, apicid_8111, 0x13);
277 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, apicid_8111, 0x10);
280 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, apicid_8111, 0x12);
281 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, apicid_8111, 0x13);
282 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, apicid_8111, 0x10);
283 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, apicid_8111, 0x11);
286 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, apicid_8111, 0x11);
287 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, apicid_8111, 0x12);
288 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, apicid_8111, 0x13);
289 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, apicid_8111, 0x10);
292 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, apicid_8111, 0x12);
293 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, apicid_8111, 0x13);
294 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, apicid_8111, 0x10);
295 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, apicid_8111, 0x11);
298 // FIXME get the irqs right, it's just hacked to work for now
299 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x11);
300 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, apicid_8111, 0x12);
301 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, apicid_8111, 0x13);
302 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, apicid_8111, 0x10);
305 // FIXME get the irqs right, it's just hacked to work for now
306 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10);
307 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11);
308 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12);
309 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13);
311 /* There is no extension information... */
313 /* Compute the checksums */
314 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
315 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
316 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
317 mc, smp_next_mpe_entry(mc));
318 return smp_next_mpe_entry(mc);
321 static void reboot_if_hotswap(void)
323 /* Hack patch work around for hot swap enable 33mhz problem */
329 unsigned bus_chain_0 = node_link_to_bus(0, 0);
332 printk(BIOS_DEBUG, "Looking for bad PCIX MHz input\n");
333 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
335 printk(BIOS_DEBUG, "Couldn't find %02x:02.0 \n", bus_chain_0);
337 data = pci_read_config32(dev, 0xa0);
338 if(!(((data>>16)&0x03)==0x03)) {
340 printk(BIOS_DEBUG, "Bad PCIX MHz - Reset\n");
343 printk(BIOS_DEBUG, "Looking for bad Hot Swap Enable\n");
344 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
346 printk(BIOS_DEBUG, "Couldn't find %02x:01.0 \n", bus_chain_0);
348 data = pci_read_config32(dev, 0x48);
351 printk(BIOS_DEBUG, "Bad Hot Swap start - Reset\n");
356 dev = dev_find_slot(node_link_to_bus(0, 0), PCI_DEVFN(0x04,3));
357 pci_write_config8(dev, 0x41, 0xf1);
359 dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
360 htic = pci_read_config32(dev, HT_INIT_CONTROL);
361 htic &= ~HTIC_BIOSR_Detect;
362 pci_write_config32(dev, HT_INIT_CONTROL, htic);
366 printk(BIOS_DEBUG, "OK 133MHz & Hot Swap is off\n");
370 unsigned long write_smp_table(unsigned long addr)
375 v = smp_write_floating_table(addr);
376 return (unsigned long)smp_write_config_table(v);