src/mainboard/arima/hdama/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include "arch/romcc_io.h"
   5 #include "pc80/serial.c"
   6 #include "arch/i386/lib/console.c"
   7 #include "ram/ramtest.c"
   8 #include "northbridge/amd/amdk8/early_ht.c"
   9 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  10 #include "northbridge/amd/amdk8/raminit.h"
  11
  12 #warning "FIXME move these delay functions somewhere more appropriate"
  13 #warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz"
  14 static void print_clock_multiplier(void)
  15 {
  16         msr_t msr;
  17         print_debug("clock multipler: 0x");
  18         msr = rdmsr(0xc0010042);
  19         print_debug_hex32(msr.lo & 0x3f);
  20         print_debug(" = 0x");
  21         print_debug_hex32(((msr.lo & 0x3f) + 8) * 100);
  22         print_debug("Mhz\r\n");
  23 }
  24
  25 static unsigned usecs_to_ticks(unsigned usecs)
  26 {
  27 #warning "FIXME make usecs_to_ticks work properly"
  28 #if 1
  29         return usecs *2000;
  30 #else
  31         /* This can only be done if cpuid says fid changing is supported
  32          * I need to look up the base frequency another way for other
  33          * cpus.  Is it worth dedicating a global register to this?
  34          * Are the PET timers useable for this purpose?
  35          */
  36         msr_t msr;
  37         msr = rdmsr(0xc0010042);
  38         return ((msr.lo & 0x3f) + 8) * 100 *usecs;
  39 #endif
  40 }
  41
  42 static void init_apic_timer(void)
  43 {
  44         volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
  45         uint32_t start, end;
  46         /* Set the apic timer to no interrupts and periodic mode */
  47         apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0);
  48         /* Set the divider to 1, no divider */
  49         apic_reg[0x3e0 >> 2] = (1 << 3) | 3;
  50         /* Set the initial counter to 0xffffffff */
  51         apic_reg[0x380 >> 2] = 0xffffffff;
  52 }
  53
  54 static void udelay(unsigned usecs)
  55 {
  56 #if 1
  57         uint32_t start, ticks;
  58         tsc_t tsc;
  59         /* Calculate the number of ticks to run for */
  60         ticks = usecs_to_ticks(usecs);
  61         /* Find the current time */
  62         tsc = rdtsc();
  63         start = tsc.lo;
  64         do {
  65                 tsc = rdtsc();
  66         } while((tsc.lo - start) < ticks);
  67 #else
  68         volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
  69         uint32_t start, value, ticks;
  70         /* Calculate the number of ticks to run for */
  71         ticks = usecs * 200;
  72         start = apic_reg[0x390 >> 2];
  73         do {
  74                 value = apic_reg[0x390 >> 2];
  75         } while((start - value) < ticks);
  76 #endif
  77 }
  78
  79 static void mdelay(unsigned msecs)
  80 {
  81         int i;
  82         for(i = 0; i < msecs; i++) {
  83                 udelay(1000);
  84         }
  85 }
  86
  87 static void delay(unsigned secs)
  88 {
  89         int i;
  90         for(i = 0; i < secs; i++) {
  91                 mdelay(1000);
  92         }
  93 }
  94
  95
  96 static void memreset_setup(const struct mem_controller *ctrl)
  97 {
  98         /* Set the memreset low */
  99         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
 100         /* Ensure the BIOS has control of the memory lines */
 101         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
 102         print_debug("memreset lo\r\n");
 103 }
 104
 105 static void memreset(const struct mem_controller *ctrl)
 106 {
 107         udelay(800);
 108         /* Set memreset_high */
 109         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
 110         print_debug("memreset hi\r\n");
 111         udelay(50);
 112 }
 113
 114
 115 #include "northbridge/amd/amdk8/raminit.c"
 116 #include "northbridge/amd/amdk8/coherent_ht.c"
 117 #include "sdram/generic_sdram.c"
 118
 119 #define NODE_ID         0x60
 120 #define HT_INIT_CONTROL 0x6c
 121
 122 #define HTIC_ColdR_Detect  (1<<4)
 123 #define HTIC_BIOSR_Detect  (1<<5)
 124 #define HTIC_INIT_Detect   (1<<6)
 125
 126 static int boot_cpu(void)
 127 {
 128         volatile unsigned long *local_apic;
 129         unsigned long apic_id;
 130         int bsp;
 131         msr_t msr;
 132         msr = rdmsr(0x1b);
 133         bsp = !!(msr.lo & (1 << 8));
 134         if (bsp) {
 135                 print_debug("Bootstrap cpu\r\n");
 136         }
 137
 138         return bsp;
 139 }
 140
 141 static int cpu_init_detected(void)
 142 {
 143         unsigned long dcl;
 144         int cpu_init;
 145
 146         unsigned long htic;
 147
 148         htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
 149 #if 0
 150         print_debug("htic: ");
 151         print_debug_hex32(htic);
 152         print_debug("\r\n");
 153
 154         if (!(htic & HTIC_ColdR_Detect)) {
 155                 print_debug("Cold Reset.\r\n");
 156         }
 157         if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
 158                 print_debug("BIOS generated Reset.\r\n");
 159         }
 160         if (htic & HTIC_INIT_Detect) {
 161                 print_debug("Init event.\r\n");
 162         }
 163 #endif
 164         cpu_init = (htic & HTIC_INIT_Detect);
 165         if (cpu_init) {
 166                 print_debug("CPU INIT Detected.\r\n");
 167         }
 168         return cpu_init;
 169 }
 170
 171
 172 static void print_debug_pci_dev(unsigned dev)
 173 {
 174         print_debug("PCI: ");
 175         print_debug_hex8((dev >> 16) & 0xff);
 176         print_debug_char(':');
 177         print_debug_hex8((dev >> 11) & 0x1f);
 178         print_debug_char('.');
 179         print_debug_hex8((dev >> 8) & 7);
 180 }
 181
 182 static void print_pci_devices(void)
 183 {
 184         device_t dev;
 185         for(dev = PCI_DEV(0, 0, 0);
 186                 dev <= PCI_DEV(0, 0x1f, 0x7);
 187                 dev += PCI_DEV(0,0,1)) {
 188                 uint32_t id;
 189                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 190                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
 191                         (((id >> 16) & 0xffff) == 0xffff) ||
 192                         (((id >> 16) & 0xffff) == 0x0000)) {
 193                         continue;
 194                 }
 195                 print_debug_pci_dev(dev);
 196                 print_debug("\r\n");
 197         }
 198 }
 199
 200
 201 static void dump_pci_device(unsigned dev)
 202 {
 203         int i;
 204         print_debug_pci_dev(dev);
 205         print_debug("\r\n");
 206
 207         for(i = 0; i <= 255; i++) {
 208                 unsigned char val;
 209                 if ((i & 0x0f) == 0) {
 210                         print_debug_hex8(i);
 211                         print_debug_char(':');
 212                 }
 213                 val = pci_read_config8(dev, i);
 214                 print_debug_char(' ');
 215                 print_debug_hex8(val);
 216                 if ((i & 0x0f) == 0x0f) {
 217                         print_debug("\r\n");
 218                 }
 219         }
 220 }
 221
 222 static void dump_pci_devices(void)
 223 {
 224         device_t dev;
 225         for(dev = PCI_DEV(0, 0, 0);
 226                 dev <= PCI_DEV(0, 0x1f, 0x7);
 227                 dev += PCI_DEV(0,0,1)) {
 228                 uint32_t id;
 229                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 230                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
 231                         (((id >> 16) & 0xffff) == 0xffff) ||
 232                         (((id >> 16) & 0xffff) == 0x0000)) {
 233                         continue;
 234                 }
 235                 dump_pci_device(dev);
 236         }
 237 }
 238
 239 static void dump_spd_registers(const struct mem_controller *ctrl)
 240 {
 241         int i;
 242         print_debug("\r\n");
 243         for(i = 0; i < 4; i++) {
 244                 unsigned device;
 245                 device = ctrl->channel0[i];
 246                 if (device) {
 247                         int j;
 248                         print_debug("dimm: ");
 249                         print_debug_hex8(i);
 250                         print_debug(".0: ");
 251                         print_debug_hex8(device);
 252                         for(j = 0; j < 256; j++) {
 253                                 int status;
 254                                 unsigned char byte;
 255                                 if ((j & 0xf) == 0) {
 256                                         print_debug("\r\n");
 257                                         print_debug_hex8(j);
 258                                         print_debug(": ");
 259                                 }
 260                                 status = smbus_read_byte(device, j);
 261                                 if (status < 0) {
 262                                         print_debug("bad device\r\n");
 263                                         break;
 264                                 }
 265                                 byte = status & 0xff;
 266                                 print_debug_hex8(byte);
 267                                 print_debug_char(' ');
 268                         }
 269                         print_debug("\r\n");
 270                 }
 271                 device = ctrl->channel1[i];
 272                 if (device) {
 273                         int j;
 274                         print_debug("dimm: ");
 275                         print_debug_hex8(i);
 276                         print_debug(".1: ");
 277                         print_debug_hex8(device);
 278                         for(j = 0; j < 256; j++) {
 279                                 int status;
 280                                 unsigned char byte;
 281                                 if ((j & 0xf) == 0) {
 282                                         print_debug("\r\n");
 283                                         print_debug_hex8(j);
 284                                         print_debug(": ");
 285                                 }
 286                                 status = smbus_read_byte(device, j);
 287                                 if (status < 0) {
 288                                         print_debug("bad device\r\n");
 289                                         break;
 290                                 }
 291                                 byte = status & 0xff;
 292                                 print_debug_hex8(byte);
 293                                 print_debug_char(' ');
 294                         }
 295                         print_debug("\r\n");
 296                 }
 297         }
 298 }
 299
 300 static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg)
 301 {
 302         outb(reg, port);
 303         outb(value, port +1);
 304 }
 305
 306 static unsigned char pnp_read_config(unsigned char port, unsigned char reg)
 307 {
 308         outb(reg, port);
 309         return inb(port +1);
 310 }
 311
 312 static void pnp_set_logical_device(unsigned char port, int device)
 313 {
 314         pnp_write_config(port, device, 0x07);
 315 }
 316
 317 static void pnp_set_enable(unsigned char port, int enable)
 318 {
 319         pnp_write_config(port, enable?0x1:0x0, 0x30);
 320 }
 321
 322 static int pnp_read_enable(unsigned char port)
 323 {
 324         return !!pnp_read_config(port, 0x30);
 325 }
 326
 327 static void pnp_set_iobase0(unsigned char port, unsigned iobase)
 328 {
 329         pnp_write_config(port, (iobase >> 8) & 0xff, 0x60);
 330         pnp_write_config(port, iobase & 0xff, 0x61);
 331 }
 332
 333 static void pnp_set_iobase1(unsigned char port, unsigned iobase)
 334 {
 335         pnp_write_config(port, (iobase >> 8) & 0xff, 0x62);
 336         pnp_write_config(port, iobase & 0xff, 0x63);
 337 }
 338
 339 static void pnp_set_irq0(unsigned char port, unsigned irq)
 340 {
 341         pnp_write_config(port, irq, 0x70);
 342 }
 343
 344 static void pnp_set_irq1(unsigned char port, unsigned irq)
 345 {
 346         pnp_write_config(port, irq, 0x72);
 347 }
 348
 349 static void pnp_set_drq(unsigned char port, unsigned drq)
 350 {
 351         pnp_write_config(port, drq & 0xff, 0x74);
 352 }
 353
 354 #define PC87360_FDC  0x00
 355 #define PC87360_PP   0x01
 356 #define PC87360_SP2  0x02
 357 #define PC87360_SP1  0x03
 358 #define PC87360_SWC  0x04
 359 #define PC87360_KBCM 0x05
 360 #define PC87360_KBCK 0x06
 361 #define PC87360_GPIO 0x07
 362 #define PC87360_ACB  0x08
 363 #define PC87360_FSCM 0x09
 364 #define PC87360_WDT  0x0A
 365
 366 static void pc87360_enable_serial(void)
 367 {
 368         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 369         pnp_set_enable(SIO_BASE, 1);
 370         pnp_set_iobase0(SIO_BASE, 0x3f8);
 371 }
 372
 373 static void main(void)
 374 {
 375         /*
 376          * GPIO28 of 8111 will control H0_MEMRESET_L
 377          * GPIO29 of 8111 will control H1_MEMRESET_L
 378          */
 379
 380         static const struct mem_controller cpu0 = {
 381                 .f0 = PCI_DEV(0, 0x18, 0),
 382                 .f1 = PCI_DEV(0, 0x18, 1),
 383                 .f2 = PCI_DEV(0, 0x18, 2),
 384                 .f3 = PCI_DEV(0, 0x18, 3),
 385                 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 386                 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 387         };
 388         static const struct mem_controller cpu1 = {
 389                 .f0 = PCI_DEV(0, 0x19, 0),
 390                 .f1 = PCI_DEV(0, 0x19, 1),
 391                 .f2 = PCI_DEV(0, 0x19, 2),
 392                 .f3 = PCI_DEV(0, 0x19, 3),
 393                 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 394                 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 395         };
 396         pc87360_enable_serial();
 397         uart_init();
 398         console_init();
 399         if (boot_cpu() && !cpu_init_detected()) {
 400 #if 1
 401                 init_apic_timer();
 402 #endif
 403                 setup_default_resource_map();
 404                 setup_coherent_ht_domain();
 405                 enumerate_ht_chain();
 406                 print_pci_devices();
 407                 enable_smbus();
 408                 dump_spd_registers(&cpu0);
 409                 sdram_initialize(&cpu0);
 410
 411 #if 0
 412                 dump_pci_devices();
 413 #endif
 414 #if 0
 415                 dump_pci_device(PCI_DEV(0, 0x18, 2));
 416 #endif
 417
 418                 /* Check all of memory */
 419                 msr_t msr;
 420                 msr = rdmsr(TOP_MEM);
 421                 print_debug("TOP_MEM: ");
 422                 print_debug_hex32(msr.hi);
 423                 print_debug_hex32(msr.lo);
 424                 print_debug("\r\n");
 425 #if 0
 426                 ram_check(0x00000000, msr.lo);
 427 #else
 428                 /* Check 16MB of memory */
 429                 ram_check(0x00000000, 0x1600000);
 430 #endif
 431 #if 0
 432                 print_debug("sleeping 15s\r\n");
 433                 delay(15);
 434                 print_debug("sleeping 15s done\r\n");
 435 #endif
 436         }
 437 }