src/mainboard/arima/hdama/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <arch/cpu.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include <cpu/amd/model_fxx_rev.h>
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  22 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24
  25 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  26
  27 /* Look up a which bus a given node/link combination is on.
  28  * return 0 when we can't find the answer.
  29  */
  30
  31 static void hard_reset(void)
  32 {
  33         device_t dev;
  34
  35         /* Find the device */
  36         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
  37
  38         /* enable cf9 */
  39         pci_write_config8(dev, 0x41, 0xf1);
  40
  41         /* reset */
  42         set_bios_reset();
  43         outb(0x0e, 0x0cf9);
  44 }
  45
  46 static void soft_reset(void)
  47 {
  48         device_t dev;
  49
  50         /* Find the device */
  51         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
  52
  53         /* Reset */
  54         set_bios_reset();
  55         pci_write_config8(dev, 0x47, 1);
  56 }
  57
  58 /*
  59  * GPIO28 of 8111 will control H0_MEMRESET_L
  60  * GPIO29 of 8111 will control H1_MEMRESET_L
  61  */
  62 static void memreset_setup(void)
  63 {
  64         if (is_cpu_pre_c0()) {
  65                 /* Set the memreset low */
  66                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  67                 /* Ensure the BIOS has control of the memory lines */
  68                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  69         }
  70         else {
  71                 /* Ensure the CPU has controll of the memory lines */
  72                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  73         }
  74 }
  75
  76 static void memreset(int controllers, const struct mem_controller *ctrl)
  77 {
  78         if (is_cpu_pre_c0()) {
  79                 udelay(800);
  80                 /* Set memreset_high */
  81                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  82                 udelay(90);
  83         }
  84 }
  85
  86 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  87 {
  88         /* Routing Table Node i
  89          *
  90          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  91          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  92          *
  93          * [ 0: 3] Request Route
  94          *     [0] Route to this node
  95          *     [1] Route to Link 0
  96          *     [2] Route to Link 1
  97          *     [3] Route to Link 2
  98          * [11: 8] Response Route
  99          *     [0] Route to this node
 100          *     [1] Route to Link 0
 101          *     [2] Route to Link 1
 102          *     [3] Route to Link 2
 103          * [19:16] Broadcast route
 104          *     [0] Route to this node
 105          *     [1] Route to Link 0
 106          *     [2] Route to Link 1
 107          *     [3] Route to Link 2
 108          */
 109
 110         uint32_t ret = 0x00010101; /* default row entry */
 111
 112         /* CPU0 LDT1 <-> LDT1 CPU1 */
 113         static const unsigned int rows_2p[2][2] = {
 114                 { 0x00050101, 0x00010404 },
 115                 { 0x00010404, 0x00050101 }
 116         };
 117
 118         if (maxnodes > 2) {
 119                 print_spew("this mainboard is only designed for 2 cpus\r\n");
 120                 maxnodes = 2;
 121         }
 122
 123         if (!(node >= maxnodes || row >= maxnodes)) {
 124                 ret = rows_2p[node][row];
 125         }
 126
 127         return ret;
 128 }
 129
 130 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 131 {
 132         /* nothing to do */
 133 }
 134
 135 static inline int spd_read_byte(unsigned device, unsigned address)
 136 {
 137         return smbus_read_byte(device, address);
 138 }
 139
 140 #include "northbridge/amd/amdk8/raminit.c"
 141 #include "northbridge/amd/amdk8/coherent_ht.c"
 142 #include "northbridge/amd/amdk8/incoherent_ht.c"
 143 #include "sdram/generic_sdram.c"
 144 #include "cpu/amd/dualcore/dualcore.c"
 145 #include "northbridge/amd/amdk8/resourcemap.c"
 146 #include "debug.c"
 147
 148 #define FIRST_CPU  1
 149 #define SECOND_CPU 1
 150 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 151
 152
 153 static void main(unsigned long bist)
 154 {
 155         static const struct mem_controller cpu[] = {
 156 #if FIRST_CPU
 157                 {
 158                         .node_id = 0,
 159                         .f0 = PCI_DEV(0, 0x18, 0),
 160                         .f1 = PCI_DEV(0, 0x18, 1),
 161                         .f2 = PCI_DEV(0, 0x18, 2),
 162                         .f3 = PCI_DEV(0, 0x18, 3),
 163                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 164                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 165                 },
 166 #endif
 167 #if SECOND_CPU
 168                 {
 169                         .node_id = 1,
 170                         .f0 = PCI_DEV(0, 0x19, 0),
 171                         .f1 = PCI_DEV(0, 0x19, 1),
 172                         .f2 = PCI_DEV(0, 0x19, 2),
 173                         .f3 = PCI_DEV(0, 0x19, 3),
 174                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 175                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 176                 },
 177 #endif
 178         };
 179
 180         int needs_reset;
 181         if (bist == 0) {
 182                 k8_init_and_stop_secondaries();
 183         }
 184         /* Setup the console */
 185         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 186         uart_init();
 187         console_init();
 188
 189         /* Halt if there was a built in self test failure */
 190         report_bist_failure(bist);
 191
 192         setup_default_resource_map();
 193         needs_reset = setup_coherent_ht_domain();
 194         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 195         if (needs_reset) {
 196                 print_info("ht reset -\r\n");
 197                 soft_reset();
 198         }
 199 #if 0
 200         print_pci_devices();
 201 #endif
 202         enable_smbus();
 203 #if 0
 204         dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu);
 205 #endif
 206
 207         memreset_setup();
 208         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 209
 210 #if 0
 211         dump_pci_devices();
 212 #endif
 213 #if 0
 214         dump_pci_device(PCI_DEV(0, 0x18, 2));
 215         dump_pci_device(PCI_DEV(0, 0x18, 3));
 216 #endif
 217
 218 #if 0
 219         /* Check the first 1M */
 220         ram_check(0x00000000, 0x000100000);
 221 #endif
 222 }