3 uses USE_FALLBACK_IMAGE
11 uses ROM_SECTION_OFFSET
12 uses CONFIG_ROM_STREAM_START
23 ## Build code for the fallback boot
25 option HAVE_FALLBACK_BOOT=1
28 ## Build code to reset the motherboard from linuxBIOS
30 option HAVE_HARD_RESET=1
33 ## Build code to export a programmable irq routing table
35 option HAVE_PIRQ_TABLE=1
36 option IRQ_SLOT_COUNT=7
39 ## Build code to export an x86 MP table
40 ## Useful for specifying IRQ routing values
42 option HAVE_MP_TABLE=1
45 ## Build code to export a CMOS option table
47 option HAVE_OPTION_TABLE=1
50 ## Build code for SMP support
51 ## Only worry about 2 micro processors
54 option CONFIG_MAX_CPUS=2
57 ## Build code to setup a generic IOAPIC
59 option CONFIG_IOAPIC=1
62 ## Clean up the motherboard id strings
64 option MAINBOARD_PART_NUMBER="HDAMA"
65 option MAINBOARD_VENDOR="ARIMA"
68 ### LinuxBIOS layout values
71 ## ROM_SIZE is the size of boot ROM that this board will use.
72 default ROM_SIZE = 524288
74 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
75 option ROM_IMAGE_SIZE = 65536
78 ## Use a small 8K stack
80 option STACK_SIZE=0x2000
83 ## Use a small 16K heap
85 option HEAP_SIZE=0x4000
88 ## Only use the option table in a normal image
90 option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
93 ## Compute the location and size of where this firmware image
94 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
97 option ROM_SECTION_SIZE = FALLBACK_SIZE
98 option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
100 option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
101 option ROM_SECTION_OFFSET = 0
105 ## Compute the start location and size size of
106 ## The linuxBIOS bootloader.
108 option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
109 option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
110 option CONFIG_ROM_STREAM = 1
113 ## Compute where this copy of linuxBIOS will start in the boot rom
115 option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
118 ## Compute a range of ROM that can cached to speed up linuxBIOS,
121 ## XIP_ROM_SIZE must be a power of 2.
122 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
124 option XIP_ROM_SIZE=65536
125 option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
128 ## Set all of the defaults for an x86 architecture
135 ## Build the objects we have code for in this directory.
140 #object static_devices.o
141 if HAVE_MP_TABLE object mptable.o end
142 if HAVE_PIRQ_TABLE object irq_tables.o end
148 makerule ./failover.E
149 depends "$(MAINBOARD)/failover.c"
150 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
153 makerule ./failover.inc
154 depends "./failover.E ./romcc"
155 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
159 depends "$(MAINBOARD)/auto.c"
160 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
163 depends "./auto.E ./romcc"
164 action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
168 ## Build our 16 bit and 32 bit linuxBIOS entry code
170 mainboardinit cpu/i386/entry16.inc
171 mainboardinit cpu/i386/entry32.inc
172 ldscript /cpu/i386/entry16.lds
173 ldscript /cpu/i386/entry32.lds
176 ## Build our reset vector (This is where linuxBIOS is entered)
178 if USE_FALLBACK_IMAGE
179 mainboardinit cpu/i386/reset16.inc
180 ldscript /cpu/i386/reset16.lds
182 mainboardinit cpu/i386/reset32.inc
183 ldscript /cpu/i386/reset32.lds
186 ### Should this be in the northbridge code?
187 mainboardinit arch/i386/lib/cpu_reset.inc
190 ## Include an id string (For safe flashing)
192 mainboardinit arch/i386/lib/id.inc
193 ldscript /arch/i386/lib/id.lds
198 mainboardinit cpu/k8/earlymtrr.inc
201 ### This is the early phase of linuxBIOS startup
202 ### Things are delicate and we test to see if we should
203 ### failover to another image.
205 if USE_FALLBACK_IMAGE
206 ldscript /arch/i386/lib/failover.lds
207 mainboardinit ./failover.inc
211 ### O.k. We aren't just an intermediary anymore!
217 mainboardinit cpu/k8/enable_mmx_sse.inc
218 mainboardinit ./auto.inc
219 mainboardinit cpu/k8/disable_mmx_sse.inc
222 ## Include the secondary Configuration files
227 northbridge amd/amdk8 "mc0"
234 southbridge amd/amd8131 "amd8131"
240 southbridge amd/amd8111 "amd8111"
260 register "com1" = "{1, 0, 0x3f8, 4}"
261 register "lpt" = "{1}"
266 northbridge amd/amdk8 "mc1"
276 register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
283 ## Include the old serial code for those few places that still need it.
285 mainboardinit pc80/serial.inc
286 mainboardinit arch/i386/lib/console.inc