2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=131072
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_MP_TABLE object mptable.o end
47 if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
55 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
61 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
62 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
63 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
64 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
73 depends "$(MAINBOARD)/failover.c ./romcc"
74 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
77 makerule ./failover.inc
78 depends "$(MAINBOARD)/failover.c ./romcc"
79 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
83 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
84 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
87 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
88 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
94 ## Build our 16 bit and 32 bit linuxBIOS entry code
97 mainboardinit cpu/x86/16bit/entry16.inc
98 ldscript /cpu/x86/16bit/entry16.lds
101 mainboardinit cpu/x86/32bit/entry32.inc
105 ldscript /cpu/x86/32bit/entry32.lds
109 ldscript /cpu/amd/car/cache_as_ram.lds
114 ## Build our reset vector (This is where linuxBIOS is entered)
116 if USE_FALLBACK_IMAGE
117 mainboardinit cpu/x86/16bit/reset16.inc
118 ldscript /cpu/x86/16bit/reset16.lds
120 mainboardinit cpu/x86/32bit/reset32.inc
121 ldscript /cpu/x86/32bit/reset32.lds
126 ### Should this be in the northbridge code?
127 mainboardinit arch/i386/lib/cpu_reset.inc
131 ## Include an id string (For safe flashing)
133 mainboardinit arch/i386/lib/id.inc
134 ldscript /arch/i386/lib/id.lds
138 ## Setup Cache-As-Ram
140 mainboardinit cpu/amd/car/cache_as_ram.inc
144 ### This is the early phase of linuxBIOS startup
145 ### Things are delicate and we test to see if we should
146 ### failover to another image.
148 if USE_FALLBACK_IMAGE
150 ldscript /arch/i386/lib/failover.lds
152 ldscript /arch/i386/lib/failover.lds
153 mainboardinit ./failover.inc
158 ### O.k. We aren't just an intermediary anymore!
169 mainboardinit ./auto.inc
177 mainboardinit cpu/x86/fpu/enable_fpu.inc
178 mainboardinit cpu/x86/mmx/enable_mmx.inc
179 mainboardinit cpu/x86/sse/enable_sse.inc
180 mainboardinit ./auto.inc
181 mainboardinit cpu/x86/sse/disable_sse.inc
182 mainboardinit cpu/x86/mmx/disable_mmx.inc
186 ## Include the secondary Configuration files
190 # config for arima/hdama
191 chip northbridge/amd/amdk8/root_complex
192 device apic_cluster 0 on
193 chip cpu/amd/socket_940
197 device pci_domain 0 on
198 chip northbridge/amd/amdk8
199 device pci 18.0 on # northbridge
200 # devices on link 0, link 0 == LDT 0
201 chip southbridge/amd/amd8131
202 # the on/off keyword is mandatory
203 device pci 0.0 on # PCIX bridge
205 #chip drivers/generic/generic
211 #chip drivers/generic/generic
217 #chip drivers/generic/generic
226 #chip drivers/generic/generic
235 device pci 0.1 on end # IOAPIC
236 device pci 1.0 on # PCIX bridge
238 #chip drivers/generic/generic
247 #chip drivers/generic/generic
256 device pci 1.1 on end # IOAPIC
258 chip southbridge/amd/amd8111
259 # this "device pci 0.0" is the parent of the next one
262 device pci 0.0 on end # USB0
263 device pci 0.1 on end # USB1
264 device pci 0.2 off end # USB 2.0
265 device pci 1.0 off end # LAN
266 chip drivers/pci/onboard
267 device pci 6.0 on end # ATI Rage XL
268 register "rom_address" = "0xfff80000"
270 ## PCI Slot 5 (correct?)
271 #chip drivers/generic/generic
279 ## PCI Slot 6 (correct?)
280 #chip drivers/generic/generic
292 chip superio/nsc/pc87360
293 device pnp 2e.0 off # Floppy
298 device pnp 2e.1 off # Parallel Port
302 device pnp 2e.2 off # Com 2
306 device pnp 2e.3 on # Com 1
310 device pnp 2e.4 off end # SWC
311 device pnp 2e.5 off end # Mouse
312 device pnp 2e.6 on # Keyboard
317 device pnp 2e.7 off end # GPIO
318 device pnp 2e.8 off end # ACB
319 device pnp 2e.9 off end # FSCM
320 device pnp 2e.a off end # WDT
323 device pci 1.1 on end # IDE
324 device pci 1.2 on end # SMBus 2.0
325 device pci 1.3 on # System Management
326 chip drivers/generic/generic
327 #phillips pca9545 smbus mux
329 # analog_devices adm1026
330 chip drivers/generic/generic
338 chip drivers/generic/generic #dimm 0-0-0
341 chip drivers/generic/generic #dimm 0-0-1
344 chip drivers/generic/generic #dimm 0-1-0
347 chip drivers/generic/generic #dimm 0-1-1
350 chip drivers/generic/generic #dimm 1-0-0
353 chip drivers/generic/generic #dimm 1-0-1
356 chip drivers/generic/generic #dimm 1-1-0
359 chip drivers/generic/generic #dimm 1-1-1
363 device pci 1.5 off end # AC97 Audio
364 device pci 1.6 on end # AC97 Modem
365 register "ide0_enable" = "1"
366 register "ide1_enable" = "1"
368 end # device pci 18.0
370 device pci 18.0 on end # LDT1
371 device pci 18.0 on end # LDT2
372 device pci 18.1 on end
373 device pci 18.2 on end
374 device pci 18.3 on end
375 end # chip northbridge/amd/amdk8
376 chip northbridge/amd/amdk8
377 device pci 19.0 on end
378 device pci 19.0 on end
379 device pci 19.0 on end
380 device pci 19.1 on end
381 device pci 19.2 on end
382 device pci 19.3 on end