src/mainboard/amd/torpedo/cfg.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #include <string.h>
  22 #include "SbPlatform.h"
  23 #include "cfg.h"
  24 #include <console/console.h>    /* printk */
  25
  26
  27 /**
  28  * @brief South Bridge CIMx configuration
  29  *
  30  * should be called before exeucte CIMx function.
  31  * this function will be called in romstage and ramstage.
  32  */
  33 void sb900_cimx_config(AMDSBCFG *sb_config)
  34 {
  35         if (!sb_config) {
  36         printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
  37                 return;
  38         }
  39     printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
  40         memset(sb_config, 0, sizeof(AMDSBCFG));
  41
  42         /* static Build Parameters */
  43         sb_config->BuildParameters.BiosSize                             = BIOS_SIZE;
  44         sb_config->BuildParameters.LegacyFree                   = LEGACY_FREE;
  45         sb_config->BuildParameters.WatchDogTimerBase    = WATCHDOG_TIMER_BASE_ADDRESS;  // Board Level
  46         sb_config->BuildParameters.AcpiGpe0BlkAddr              = GPE0_BLK_ADDRESS;                             // Board Level
  47         sb_config->BuildParameters.CpuControlBlkAddr    = CPU_CNT_BLK_ADDRESS;                  // Board Level
  48         sb_config->BuildParameters.AcpiPmTmrBlkAddr             = PM1_TMR_BLK_ADDRESS;                  // Board Level
  49         sb_config->BuildParameters.AcpiPm1CntBlkAddr    = PM1_CNT_BLK_ADDRESS;                  // Board Level
  50         sb_config->BuildParameters.AcpiPm1EvtBlkAddr    = PM1_EVT_BLK_ADDRESS;                  // Board Level
  51         sb_config->BuildParameters.SioPmeBaseAddress    = SIO_PME_BASE_ADDRESS;                 // Board Level
  52         sb_config->BuildParameters.SpiRomBaseAddress    = SPI_BASE_ADDRESS;                             // Board Level
  53         sb_config->BuildParameters.Smbus0BaseAddress    = SMBUS0_BASE_ADDRESS;                  // Board Level
  54         sb_config->BuildParameters.Smbus1BaseAddress    = SMBUS1_BASE_ADDRESS;                  // Board Level
  55
  56         /* Turn on CDROM and HDD Power */
  57         sb_config->SATAMODE.SataMode.SataClkMode                = SATA_CLK_RESERVED;
  58
  59         // header
  60         sb_config->StdHeader.PcieBasePtr                                = PCIEX_BASE_ADDRESS;
  61
  62         // Build Parameters
  63         sb_config->BuildParameters.ImcEnableOverWrite   = IMC_ENABLE_OVER_WRITE;                // Internal Option
  64         sb_config->BuildParameters.UsbMsi                               = USB_MSI;                                              // Internal Option
  65         sb_config->BuildParameters.HdAudioMsi                   = HDAUDIO_MSI;                                  // Internal Option
  66         sb_config->BuildParameters.LpcMsi                               = LPC_MSI;                                              // Internal Option
  67         sb_config->BuildParameters.PcibMsi                              = PCIB_MSI;                                             // Internal Option
  68         sb_config->BuildParameters.AbMsi                                = AB_MSI;                                               // Internal Option
  69         sb_config->BuildParameters.GecShadowRomBase             = GEC_SHADOWROM_BASE;                   // Board Level
  70         sb_config->BuildParameters.HpetBase                             = HPET_BASE_ADDRESS;                    // Board Level
  71         sb_config->BuildParameters.SataIDESsid                  = SATA_IDE_MODE_SSID;                   // Board Level
  72         sb_config->BuildParameters.SataRAIDSsid                 = SATA_RAID_MODE_SSID;                  // Board Level
  73         sb_config->BuildParameters.SataRAID5Ssid                = SATA_RAID5_MODE_SSID;                 // Board Level
  74         sb_config->BuildParameters.SataAHCISsid                 = SATA_AHCI_SSID;                               // Board Level
  75         sb_config->BuildParameters.OhciSsid                             = OHCI_SSID;                                    // Board Level
  76         sb_config->BuildParameters.EhciSsid                             = EHCI_SSID;                                    // Board Level
  77         sb_config->BuildParameters.Ohci4Ssid                    = OHCI4_SSID;                                   // Board Level
  78         sb_config->BuildParameters.SmbusSsid                    = SMBUS_SSID;                                   // Board Level
  79         sb_config->BuildParameters.IdeSsid                              = IDE_SSID;                                             // Board Level
  80         sb_config->BuildParameters.AzaliaSsid                   = AZALIA_SSID;                                  // Board Level
  81         sb_config->BuildParameters.LpcSsid                              = LPC_SSID;                                             // Board Level
  82         // sb_config->BuildParameters.PCIBSsid                          = PCIB_SSID;                                    // Field Retired
  83
  84         //
  85         // Common Function
  86         //
  87         sb_config->SATAMODE.SataMode.SataController             = SATA_CONTROLLER;                              // External Option
  88         sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt     = SATA_IDE_COMBMD_PRISEC_OPT;   // External Option
  89         sb_config->SATAMODE.SataMode.SataIdeCombinedMode        = SATA_IDECOMBINED_MODE;        // External Option
  90         sb_config->S3Resume                                                             = 0;                                                    // CIMx Internal Used
  91         sb_config->SpreadSpectrum                                               = INCHIP_SPREAD_SPECTRUM;               // Board Level
  92         sb_config->NbSbGen2                                                             = INCHIP_NB_SB_GEN2;                    // External Option
  93         sb_config->GppGen2                                                              = INCHIP_GPP_GEN2;                              // External Option
  94         sb_config->GppMemWrImprove                                              = INCHIP_GPP_MEMORY_WRITE_IMPROVE;      // Internal Option
  95         sb_config->S4Resume                                                             = 0;                                                    // CIMx Internal Used
  96         sb_config->SataClass                                                    = CONFIG_SATA_CONTROLLER_MODE;  // INCHIP_SATA_MODE     // External Option
  97         sb_config->SataIdeMode                                                  = INCHIP_IDE_MODE;                              // External Option
  98         sb_config->sdConfig                                                             = SB_SD_CONFIG;                                 // External Option
  99         sb_config->sdSpeed                                                              = SB_SD_SPEED;                                  // Internal Option
 100         sb_config->sdBitwidth                                                   = SB_SD_BITWIDTH;                               // Internal Option
 101         sb_config->SataDisUnusedIdePChannel                             = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option
 102         sb_config->SataDisUnusedIdeSChannel                             = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option
 103         sb_config->IdeDisUnusedIdePChannel                              = IDE_DISUNUSED_IDE_P_CHANNEL;  // External Option
 104         sb_config->IdeDisUnusedIdeSChannel                              = IDE_DISUNUSED_IDE_S_CHANNEL;  // External Option
 105         sb_config->SATAESPPORT.SataEspPort.PORT0                = SATA_ESP_PORT0;                               // Board Level
 106         sb_config->SATAESPPORT.SataEspPort.PORT1                = SATA_ESP_PORT1;                               // Board Level
 107         sb_config->SATAESPPORT.SataEspPort.PORT2                = SATA_ESP_PORT2;                               // Board Level
 108         sb_config->SATAESPPORT.SataEspPort.PORT3                = SATA_ESP_PORT3;                               // Board Level
 109         sb_config->SATAESPPORT.SataEspPort.PORT4                = SATA_ESP_PORT4;                               // Board Level
 110         sb_config->SATAESPPORT.SataEspPort.PORT5                = SATA_ESP_PORT5;                               // Board Level
 111         sb_config->SATAESPPORT.SataEspPort.PORT6                = SATA_ESP_PORT6;                               // Board Level
 112         sb_config->SATAESPPORT.SataEspPort.PORT7                = SATA_ESP_PORT7;                               // Board Level
 113         sb_config->SATAPORTPOWER.SataPortPower.PORT0    = SATA_PORT_POWER_PORT0;                // Board Level
 114         sb_config->SATAPORTPOWER.SataPortPower.PORT1    = SATA_PORT_POWER_PORT1;                // Board Level
 115         sb_config->SATAPORTPOWER.SataPortPower.PORT2    = SATA_PORT_POWER_PORT2;                // Board Level
 116         sb_config->SATAPORTPOWER.SataPortPower.PORT3    = SATA_PORT_POWER_PORT3;                // Board Level
 117         sb_config->SATAPORTPOWER.SataPortPower.PORT4    = SATA_PORT_POWER_PORT4;                // Board Level
 118         sb_config->SATAPORTPOWER.SataPortPower.PORT5    = SATA_PORT_POWER_PORT5;                // Board Level
 119         sb_config->SATAPORTPOWER.SataPortPower.PORT6    = SATA_PORT_POWER_PORT6;                // Board Level
 120         sb_config->SATAPORTPOWER.SataPortPower.PORT7    = SATA_PORT_POWER_PORT7;                // Board Level
 121         sb_config->SATAPORTMODE.SataPortMd.PORT0                = SATA_PORTMODE_PORT0;                  // Board Level
 122         sb_config->SATAPORTMODE.SataPortMd.PORT1                = SATA_PORTMODE_PORT1;                  // Board Level
 123         sb_config->SATAPORTMODE.SataPortMd.PORT2                = SATA_PORTMODE_PORT2;                  // Board Level
 124         sb_config->SATAPORTMODE.SataPortMd.PORT3                = SATA_PORTMODE_PORT3;                  // Board Level
 125         sb_config->SATAPORTMODE.SataPortMd.PORT4                = SATA_PORTMODE_PORT4;                  // Board Level
 126         sb_config->SATAPORTMODE.SataPortMd.PORT5                = SATA_PORTMODE_PORT5;                  // Board Level
 127         sb_config->SATAPORTMODE.SataPortMd.PORT6                = SATA_PORTMODE_PORT6;                  // Board Level
 128         sb_config->SATAPORTMODE.SataPortMd.PORT7                = SATA_PORTMODE_PORT7;                  // Board Level
 129         sb_config->SataAggrLinkPmCap                                    = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option
 130         sb_config->SataPortMultCap                                              = INCHIP_SATA_PORT_MULT_CAP;    // Internal Option
 131         sb_config->SataClkAutoOff                                               = INCHIP_SATA_CLK_AUTO_OFF;             // External Option
 132         sb_config->SataPscCap                                                   = INCHIP_SATA_PSC_CAP;                  // External Option
 133         sb_config->SataFisBasedSwitching                                = INCHIP_SATA_FIS_BASE_SW;              // External Option
 134         sb_config->SataCccSupport                                               = INCHIP_SATA_CCC_SUPPORT;              // External Option
 135         sb_config->SataSscCap                                                   = INCHIP_SATA_SSC_CAP;                  // External Option
 136         sb_config->SataMsiCapability                                    = INCHIP_SATA_MSI_CAP;                  // Internal Option
 137         sb_config->SataForceRaid                                                = INCHIP_SATA_FORCE_RAID5;              // Internal Option
 138         sb_config->SataTargetSupport8Device                             = CIMXSB_SATA_TARGET_8DEVICE_CAP;       // External Option
 139         sb_config->SataDisableGenericMode                               = SATA_DISABLE_GENERIC_MODE_CAP;// External Option
 140         sb_config->SataAhciEnclosureManagement                  = SATA_AHCI_ENCLOSURE_CAP;              // Internal Option
 141         sb_config->SataSgpio0                                                   = SATA_GPIO_0_CAP;                              // External Option
 142         sb_config->SataSgpio1                                                   = SATA_GPIO_1_CAP;                              // External Option
 143         sb_config->SataPhyPllShutDown                                   = SATA_PHY_PLL_SHUTDOWN;                // External Option
 144         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0;    // Board Level
 145         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1;    // Board Level
 146         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2;    // Board Level
 147         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3;    // Board Level
 148         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4;    // Board Level
 149         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5;    // Board Level
 150         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6;    // Board Level
 151         sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7;    // Board Level
 152         // USB
 153         sb_config->USBMODE.UsbMode.Ohci1                                = INCHIP_USB_OHCI1_CINFIG;              // External Option
 154         sb_config->USBMODE.UsbMode.Ehci1                                = INCHIP_USB_EHCI1_CINFIG;              // Internal Option*
 155         sb_config->USBMODE.UsbMode.Ohci2                                = INCHIP_USB_OHCI2_CINFIG;              // External Option
 156         sb_config->USBMODE.UsbMode.Ehci2                                = INCHIP_USB_EHCI2_CINFIG;              // Internal Option*
 157         sb_config->USBMODE.UsbMode.Ohci3                                = INCHIP_USB_OHCI3_CINFIG;              // External Option
 158         sb_config->USBMODE.UsbMode.Ehci3                                = INCHIP_USB_EHCI3_CINFIG;              // Internal Option*
 159         sb_config->USBMODE.UsbMode.Ohci4                                = INCHIP_USB_OHCI4_CINFIG;              // External Option
 160         // GEC
 161         sb_config->GecConfig                                                    = INCHIP_GEC_CONTROLLER;                // External Option
 162         sb_config->IrConfig                                                             = SB_IR_CONTROLLER;                             // External Option
 163         sb_config->XhciSwitch                                                   = SB_XHCI_SWITCH;                               // External Option
 164         // Azalia
 165         sb_config->AzaliaController                                             = INCHIP_AZALIA_CONTROLLER;             // External Option
 166         sb_config->AzaliaPinCfg                                                 = INCHIP_AZALIA_PIN_CONFIG;             // Board Level
 167         sb_config->FrontPanelDetected                                   = INCHIP_FRONT_PANEL_DETECTED;  // Board Level
 168         sb_config->AZALIACONFIG.AzaliaSdinPin                   = AZALIA_PIN_CONFIG;                    // Board Level
 169         sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr             = NULL;                                                 // Board Level
 170         sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL;                                                 // Board Level
 171         sb_config->AnyHT200MhzLink                                              = INCHIP_ANY_HT_200MHZ_LINK;    // Internal Option
 172         sb_config->HpetTimer                                                    = SB_HPET_TIMER;                                // External Option
 173         sb_config->AzaliaSnoop                                                  = INCHIP_AZALIA_SNOOP;                  // Internal Option*
 174         // Generic
 175         sb_config->NativePcieSupport                                    = INCHIP_NATIVE_PCIE_SUPPOORT;  // External Option
 176         // USB
 177         sb_config->UsbPhyPowerDown                                              = INCHIP_USB_PHY_POWER_DOWN;    // External Option
 178         sb_config->PcibClkStopOverride                                  = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option
 179         // sb_config->HpetMsiDis                                                        = 0;                                                            // Field Retired
 180         // sb_config->ResetCpuOnSyncFlood                                       = 0;                                                            // Field Retired
 181         // sb_config->PcibAutoClkCtr                                            = 0;                                                            // Field Retired
 182         sb_config->OEMPROGTBL.OemProgrammingTablePtr    = NULL;                                                 // Board Level
 183         sb_config->PORTCONFIG[0].PortCfg.PortPresent    = SB_GPP_PORT0;                                 // Board Level
 184         sb_config->PORTCONFIG[0].PortCfg.PortDetected   = 0;                                                    // CIMx Internal Used
 185         sb_config->PORTCONFIG[0].PortCfg.PortIsGen2             = 0;                                                    // CIMx Internal Used
 186         sb_config->PORTCONFIG[0].PortCfg.PortHotPlug    = 0;                                                    // CIMx Internal Used
 187         // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap         = 0;                                                            // Field Retired
 188         sb_config->PORTCONFIG[1].PortCfg.PortPresent    = SB_GPP_PORT1;                                 // Board Level
 189         sb_config->PORTCONFIG[1].PortCfg.PortDetected   = 0;                                                    // CIMx Internal Used
 190         sb_config->PORTCONFIG[1].PortCfg.PortIsGen2             = 0;                                                    // CIMx Internal Used
 191         sb_config->PORTCONFIG[1].PortCfg.PortHotPlug    = 0;                                                    // CIMx Internal Used
 192         // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap         = 0;                                                            // Field Retired
 193         sb_config->PORTCONFIG[2].PortCfg.PortPresent    = SB_GPP_PORT2;                                 // Board Level
 194         sb_config->PORTCONFIG[2].PortCfg.PortDetected   = 0;                                                    // CIMx Internal Used
 195         sb_config->PORTCONFIG[2].PortCfg.PortIsGen2             = 0;                                                    // CIMx Internal Used
 196         sb_config->PORTCONFIG[2].PortCfg.PortHotPlug    = 0;                                                    // CIMx Internal Used
 197         // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap         = 0;                                                            // Field Retired
 198         sb_config->PORTCONFIG[3].PortCfg.PortPresent    = SB_GPP_PORT3;                                 // Board Level
 199         sb_config->PORTCONFIG[3].PortCfg.PortDetected   = 0;                                                    // CIMx Internal Used
 200         sb_config->PORTCONFIG[3].PortCfg.PortIsGen2             = 0;                                                    // CIMx Internal Used
 201         sb_config->PORTCONFIG[3].PortCfg.PortHotPlug    = 0;                                                    // CIMx Internal Used
 202         // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap         = 0;                                                            // Field Retired
 203         sb_config->GppLinkConfig                                                = INCHIP_GPP_LINK_CONFIG;               // External Option
 204         sb_config->GppFoundGfxDev                                               = 0;                                                    // CIMx Internal Used
 205         sb_config->GppFunctionEnable                                    = SB_GPP_CONTROLLER;                    // External Option
 206         sb_config->GppUnhidePorts                                               = INCHIP_GPP_UNHIDE_PORTS;              // Internal Option
 207         sb_config->GppPortAspm                                                  = INCHIP_GPP_PORT_ASPM;                 // Internal Option
 208         sb_config->GppLaneReversal                                              = INCHIP_GPP_LANEREVERSAL;              // External Option
 209         sb_config->AlinkPhyPllPowerDown                                 = INCHIP_ALINK_PHY_PLL_POWER_DOWN;      // External Option
 210         sb_config->GppPhyPllPowerDown                                   = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option
 211         sb_config->GppDynamicPowerSaving                                = INCHIP_GPP_DYNAMIC_POWER_SAVING;      // External Option
 212         sb_config->PcieAER                                                              = INCHIP_PCIE_AER;                              // External Option
 213         sb_config->PcieRAS                                                              = INCHIP_PCIE_RAS;                              // External Option
 214         sb_config->GppHardwareDowngrade                                 = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
 215         sb_config->GppToggleReset                                               = INCHIP_GPP_TOGGLE_RESET;              // External Option
 216         sb_config->sdbEnable                                                    = 0;                                                    // CIMx Internal Used
 217         sb_config->TempMMIO                                                             = NULL;                                                 // CIMx Internal Used
 218         // sb_config->GecPhyStatus                                                      = INCHIP_GEC_PHY_STATUS;                // Field Retired
 219         sb_config->SBGecPwr                                                             = INCHIP_GEC_POWER_POLICY;              // Internal Option
 220         sb_config->SBGecDebugBus                                                = INCHIP_GEC_DEBUGBUS;                  // Internal Option
 221         sb_config->SbPcieOrderRule                                              = INCHIP_SB_PCIE_ORDER_RULE;    // External Option
 222         sb_config->AcDcMsg                                                              = INCHIP_ACDC_MSG;                              // Internal Option
 223         sb_config->TimerTickTrack                                               = INCHIP_TIMER_TICK_TRACK;              // Internal Option
 224         sb_config->ClockInterruptTag                                    = INCHIP_CLOCK_INTERRUPT_TAG;   // Internal Option
 225         sb_config->OhciTrafficHanding                                   = INCHIP_OHCI_TRAFFIC_HANDING;  // Internal Option
 226         sb_config->EhciTrafficHanding                                   = INCHIP_EHCI_TRAFFIC_HANDING;  // Internal Option
 227         sb_config->FusionMsgCMultiCore                                  = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option
 228         sb_config->FusionMsgCStage                                              = INCHIP_FUSION_MSGC_STAGE;             // Internal Option
 229         sb_config->ALinkClkGateOff                                              = INCHIP_ALINK_CLK_GATE_OFF;    // External Option
 230         sb_config->BLinkClkGateOff                                              = INCHIP_BLINK_CLK_GATE_OFF;    // External Option
 231         // sb_config->sdb                                                                       = 0;                                                            // Field Retired
 232         sb_config->GppGen2Strap                                                 = 0;                                                    // CIMx Internal Used
 233         sb_config->SlowSpeedABlinkClock                                 = INCHIP_SLOW_SPEED_ABLINK_CLOCK;       // Internal Option
 234         sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr       = NULL;                                         // Board Level
 235         sb_config->AbClockGating                                                = INCHIP_AB_CLOCK_GATING;               // External Option
 236         sb_config->GppClockGating                                               = INCHIP_GPP_CLOCK_GATING;              // External Option
 237         sb_config->L1TimerOverwrite                                             = INCHIP_L1_TIMER_OVERWRITE;    // Internal Option
 238         // sb_config->UmiLinkWidth                                                      = 0;                                                            // Field Retired
 239         sb_config->UmiDynamicSpeedChange                                = INCHIP_UMI_DYNAMIC_SPEED_CHANGE;      // Internal Option
 240         // sb_config->PcieRefClockOverclocking                          = 0;                                                            // Field Retired
 241         sb_config->SbAlinkGppTxDriverStrength                   = INCHIP_ALINK_GPP_TX_DRV_STRENGTH;     // Internal Option
 242         sb_config->PwrFailShadow                                                = 0x02;                                                 // Board Level
 243         sb_config->StressResetMode                                              = INCHIP_STRESS_RESET_MODE;             // Internal Option
 244         sb_config->hwm.fanSampleFreqDiv                                 = 0x03;                                                 // Board Level
 245         sb_config->hwm.hwmSbtsiAutoPoll                                 = 1;                                                    // Board Level
 246
 247         /* General */
 248         sb_config->PciClks                                                              = SB_PCI_CLOCK_RESERVED;
 249         sb_config->hwm.hwmEnable                                                = 0x0;
 250
 251 #ifndef __PRE_RAM__
 252         /* ramstage cimx config here */
 253         if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
 254                 sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
 255         }
 256
 257         //sb_config->
 258 #endif //!__PRE_RAM__
 259     printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
 260 }
 261
 262 void SbPowerOnInit_Config(AMDSBCFG *sb_config)
 263 {
 264         if (!sb_config) {
 265         printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
 266                 return;
 267         }
 268     printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
 269         memset(sb_config, 0, sizeof(AMDSBCFG));
 270
 271     // Set the build parameters
 272         sb_config->BuildParameters.BiosSize                             = BIOS_SIZE;                                    // Field Retired
 273         sb_config->BuildParameters.LegacyFree                   = SBCIMx_LEGACY_FREE;                   // Board Level
 274         sb_config->BuildParameters.SpiSpeed                             = SBCIMX_SPI_SPEED;                             // Internal Option
 275         sb_config->BuildParameters.SpiFastSpeed                 = SBCIMX_SPI_FASTSPEED;                 // Internal Option
 276         // sb_config->BuildParameters.SpiWriteSpeed                     =  0;                                                   // Field Retired
 277         sb_config->BuildParameters.SpiMode                              = SBCIMX_SPI_MODE;                              // Internal Option
 278         sb_config->BuildParameters.SpiBurstWrite                = SBCIMX_SPI_BURST_WRITE;               // Internla Option
 279         sb_config->BuildParameters.EcKbd                                = INCHIP_EC_KBD;                                // Board Level
 280         sb_config->BuildParameters.Smbus0BaseAddress    = SMBUS0_BASE_ADDRESS;                  // Board Level
 281         sb_config->BuildParameters.Smbus1BaseAddress    = SMBUS1_BASE_ADDRESS;                  // Board Level
 282         sb_config->BuildParameters.SioPmeBaseAddress    = SIO_PME_BASE_ADDRESS;                 // Board Level
 283         sb_config->BuildParameters.WatchDogTimerBase    = WATCHDOG_TIMER_BASE_ADDRESS;  // Board Level
 284         sb_config->BuildParameters.GecShadowRomBase             = GEC_ROM_SHADOW_ADDRESS;               // Board Level
 285         sb_config->BuildParameters.SpiRomBaseAddress    = SPI_BASE_ADDRESS;                             // Board Level
 286         sb_config->BuildParameters.AcpiPm1EvtBlkAddr    = PM1_EVT_BLK_ADDRESS;                  // Board Level
 287         sb_config->BuildParameters.AcpiPm1CntBlkAddr    = PM1_CNT_BLK_ADDRESS;                  // Board Level
 288         sb_config->BuildParameters.AcpiPmTmrBlkAddr             = PM1_TMR_BLK_ADDRESS;                  // Board Level
 289         sb_config->BuildParameters.CpuControlBlkAddr    = CPU_CNT_BLK_ADDRESS;                  // Board Level
 290         sb_config->BuildParameters.AcpiGpe0BlkAddr              = GPE0_BLK_ADDRESS;                             // Board Level
 291         sb_config->BuildParameters.SmiCmdPortAddr               = SMI_CMD_PORT;                                 // Board Level
 292         sb_config->BuildParameters.AcpiPmaCntBlkAddr    = ACPI_PMA_CNT_BLK_ADDRESS;             // Board Level
 293     sb_config->SATAMODE.SataMode.SataController         = INCHIP_SATA_CONTROLLER;               // External Option
 294     sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option
 295     sb_config->SATAMODE.SataMode.SataSetMaxGen2         = SATA_MAX_GEN2_MODE;                   // External Option
 296     sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE;                        // External Option
 297     sb_config->SATAMODE.SataMode.SataClkMode            = SATA_CLK_RESERVED;                    // Internal Option
 298     sb_config->NbSbGen2                                                         = NB_SB_GEN2;                                   // External Option
 299     sb_config->SataInternal100Spread                            = INCHIP_SATA_INTERNAL_100_SPREAD;      // External Option
 300     sb_config->OEMPROGTBL.OemProgrammingTablePtr        = NULL;                                                 // Board Level
 301     sb_config->sdbEnable                                                        = 0;                                                    // CIMx Internal Used
 302     sb_config->Cg2Pll                                                           = INCHIP_CG2_PLL;                               // Internal Option
 303
 304     printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n");
 305 }
 306
 307