2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <device/pci.h>
26 #include <cpu/amd/amdfam10_sysconf.h>
29 extern u8 bus_rs780[11];
30 extern u8 bus_sb700[2];
32 extern u32 apicid_sb700;
34 extern u32 bus_type[256];
35 extern u32 sbdn_rs780;
36 extern u32 sbdn_sb700;
38 static void *smp_write_config_table(void *v)
40 struct mp_config_table *mc;
43 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
45 mptable_init(mc, "TILAPIA ", LAPIC_ADDR);
47 smp_write_processors(mc);
51 /* Bus: Bus ID Type */
52 /* define bus and isa numbers */
53 for (j = 0; j < bus_isa; j++) {
54 smp_write_bus(mc, j, (char *)"PCI ");
56 smp_write_bus(mc, bus_isa, (char *)"ISA ");
58 /* I/O APICs: APIC ID Version State Address */
65 dev_find_slot(bus_sb700[0],
66 PCI_DEVFN(sbdn_sb700 + 0x14, 0));
68 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
69 smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
71 /* Initialize interrupt mapping */
73 byte = pci_read_config8(dev, 0x63);
75 byte |= 0; /* 0: INTA, ...., 7: INTH */
76 pci_write_config8(dev, 0x63, byte);
79 dword = pci_read_config32(dev, 0xac);
81 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
82 /* dword |= 1<<22; PIC and APIC co exists */
83 pci_write_config32(dev, 0xac, dword);
86 * 00:12.0: PROG SATA : INT F
94 * 00:14.2: Prog HDA : INT E
101 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
102 #define IO_LOCAL_INT(type, intr, apicid, pin) \
103 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
105 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
107 /* PCI interrupts are level triggered, and are
108 * associated with a specific bus/device/function tuple.
110 #if CONFIG_GENERATE_ACPI_TABLES == 0
111 #define PCI_INT(bus, dev, fn, pin) \
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
114 #define PCI_INT(bus, dev, fn, pin)
118 PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
119 PCI_INT(0x0, 0x12, 0x1, 0x11);
120 PCI_INT(0x0, 0x13, 0x0, 0x12);
121 PCI_INT(0x0, 0x13, 0x1, 0x13);
122 PCI_INT(0x0, 0x14, 0x0, 0x10);
125 PCI_INT(0x0, 0x11, 0x0, 0x16);
127 /* HD Audio: b0:d20:f1:reg63 should be 0. */
128 /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
130 /* on board NIC & Slot PCIE. */
131 /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
132 /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
133 PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
134 /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
135 PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
136 /* configuration B doesnt need dev 5,6,7 */
138 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
139 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
140 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
142 PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
143 PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
147 PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
148 PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
149 PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
150 PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
153 PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
154 PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
155 PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
156 PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
159 PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
160 PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
161 PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
162 PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
164 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
165 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
166 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
167 /* There is no extension information... */
169 /* Compute the checksums */
171 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
172 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
173 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
174 mc, smp_next_mpe_entry(mc));
175 return smp_next_mpe_entry(mc);
178 unsigned long write_smp_table(unsigned long addr)
181 v = smp_write_floating_table(addr);
182 return (unsigned long)smp_write_config_table(v);