75e66c1d03097559500ffef7806534f5cf71dce3
[coreboot.git] / src / mainboard / amd / solo / mainboard.c
1
2 #include <console/console.h>
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <device/pci_ops.h>
7
8 #include <arch/io.h>
9 #include "../../../northbridge/amd/amdk8/northbridge.h"
10 #include "chip.h"
11
12
13 unsigned long initial_apicid[CONFIG_MAX_CPUS] = {
14         0,
15 };
16
17 static struct device_operations mainboard_operations = {
18         .read_resources = root_dev_read_resources,
19         .set_resources = root_dev_set_resources,
20         .enable_resources = enable_childrens_resources,
21         .init = 0,
22         .scan_bus = amdk8_scan_root_bus,
23         .enable = 0,
24 };
25
26 static void enumerate(struct chip *chip)
27 {
28         struct chip *child;
29         dev_root.ops = &mainboard_operations;
30         chip->dev = &dev_root;
31         chip->bus = 0;
32         for (child = chip->children; child; child = child->next) {
33                 child->bus = &dev_root.link[0];
34         }
35 }
36 struct chip_control mainboard_amd_solo_control = {
37         .enumerate = enumerate,
38         .name = "AMD Solo7 mainboard ",
39 };