1 #include <arch/pirq_routing.h>
2 #include <device/pci.h>
4 #define IRQ_ROUTER_BUS 1
5 #define IRQ_ROUTER_DEVFN PCI_DEVFN(5,0)
6 #define IRQ_ROUTER_VENDOR 0x1022
7 #define IRQ_ROUTER_DEVICE 0x7468
8 #define IRQS_EXCLUSIVE 0x0c20
9 #define IRQS_AVAILABLE 0xdeb8
12 #define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
13 { bus, (dev<<3)|fn, {{ linka, IRQS_AVAILABLE}, { linkb, IRQS_AVAILABLE}, \
14 {linkc, IRQS_AVAILABLE}, {linkd, IRQS_AVAILABLE}}, slot, 0}
16 /* Each IRQ_SLOT entry consists of:
17 * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
20 const struct irq_routing_table intel_irq_routing_table = {
21 PIRQ_SIGNATURE, /* u32 signature */
22 PIRQ_VERSION, /* u16 version */
23 32 + 16 * IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
24 * devices on the bus */
25 IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
26 IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
27 IRQS_EXCLUSIVE, /* IRQs devoted exclusively to PCI usage */
28 IRQ_ROUTER_VENDOR, /* Vendor */
29 IRQ_ROUTER_DEVICE, /* Device */
30 0x00, /* Crap (miniport) */
31 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
32 0x00, /* u8 checksum , mod 256 checksum must give
33 * zero, will be corrected later
37 /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
40 IRQ_SLOT(1, 3, 4, 0, 1, 2, 3, 4),
41 IRQ_SLOT(2, 3, 5, 0, 2, 3, 4, 1),
42 IRQ_SLOT(3, 3, 6, 0, 3, 4, 1, 2),
43 IRQ_SLOT(4, 3, 7, 0, 4, 1, 2, 3),
46 IRQ_SLOT(0, 3, 0, 0, 4, 4, 4, 4), /* USB */
47 IRQ_SLOT(0, 1, 5, 1, 1, 2, 3, 4), /* IDE */
48 IRQ_SLOT(0, 1, 2, 0, 1, 2, 3, 4), /* AGP Bridge */
50 /* Let Linux know about bus 1 */
51 IRQ_SLOT(0, 1, 5, 0, 0, 0, 0, 0),
56 unsigned long write_pirq_routing_table(unsigned long addr)
58 return copy_pirq_routing_table(addr);