src/mainboard/amd/solo/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include "arch/romcc_io.h"
   5 #include "pc80/serial.c"
   6 #include "arch/i386/lib/console.c"
   7 #include "ram/ramtest.c"
   8 #include "northbridge/amd/amdk8/early_ht.c"
   9 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  10 #include "northbridge/amd/amdk8/raminit.c"
  11 #include "northbridge/amd/amdk8/coherent_ht.c"
  12 #include "sdram/generic_sdram.c"
  13
  14 #define NODE_ID         0x60
  15 #define HT_INIT_CONTROL 0x6c
  16
  17 #define HTIC_ColdR_Detect  (1<<4)
  18 #define HTIC_BIOSR_Detect  (1<<5)
  19 #define HTIC_INIT_Detect   (1<<6)
  20
  21 static int boot_cpu(void)
  22 {
  23         volatile unsigned long *local_apic;
  24         unsigned long apic_id;
  25         int bsp;
  26         msr_t msr;
  27         msr = rdmsr(0x1b);
  28         bsp = !!(msr.lo & (1 << 8));
  29         if (bsp) {
  30                 print_debug("Bootstrap processor\r\n");
  31         } else {
  32                 print_debug("Application processor\r\n");
  33         }
  34
  35         return bsp;
  36 }
  37
  38 static int cpu_init_detected(void)
  39 {
  40         unsigned long dcl;
  41         int cpu_init;
  42
  43         unsigned long htic;
  44
  45         htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
  46 #if 0
  47         print_debug("htic: ");
  48         print_debug_hex32(htic);
  49         print_debug("\r\n");
  50
  51         if (!(htic & HTIC_ColdR_Detect)) {
  52                 print_debug("Cold Reset.\r\n");
  53         }
  54         if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
  55                 print_debug("BIOS generated Reset.\r\n");
  56         }
  57         if (htic & HTIC_INIT_Detect) {
  58                 print_debug("Init event.\r\n");
  59         }
  60 #endif
  61         cpu_init = (htic & HTIC_INIT_Detect);
  62         if (cpu_init) {
  63                 print_debug("CPU INIT Detected.\r\n");
  64         }
  65         return cpu_init;
  66 }
  67
  68
  69 static void print_debug_pci_dev(unsigned dev)
  70 {
  71         print_debug("PCI: ");
  72         print_debug_hex8((dev >> 16) & 0xff);
  73         print_debug_char(':');
  74         print_debug_hex8((dev >> 11) & 0x1f);
  75         print_debug_char('.');
  76         print_debug_hex8((dev >> 8) & 7);
  77 }
  78
  79 static void print_pci_devices(void)
  80 {
  81         device_t dev;
  82         for(dev = PCI_DEV(0, 0, 0);
  83                 dev <= PCI_DEV(0, 0x1f, 0x7);
  84                 dev += PCI_DEV(0,0,1)) {
  85                 uint32_t id;
  86                 id = pci_read_config32(dev, PCI_VENDOR_ID);
  87                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  88                         (((id >> 16) & 0xffff) == 0xffff) ||
  89                         (((id >> 16) & 0xffff) == 0x0000)) {
  90                         continue;
  91                 }
  92                 print_debug_pci_dev(dev);
  93                 print_debug("\r\n");
  94         }
  95 }
  96
  97
  98 static void dump_pci_device(unsigned dev)
  99 {
 100         int i;
 101         print_debug_pci_dev(dev);
 102         print_debug("\r\n");
 103
 104         for(i = 0; i <= 255; i++) {
 105                 unsigned char val;
 106                 if ((i & 0x0f) == 0) {
 107                         print_debug_hex8(i);
 108                         print_debug_char(':');
 109                 }
 110                 val = pci_read_config8(dev, i);
 111                 print_debug_char(' ');
 112                 print_debug_hex8(val);
 113                 if ((i & 0x0f) == 0x0f) {
 114                         print_debug("\r\n");
 115                 }
 116         }
 117 }
 118
 119 static void dump_spd_registers(const struct mem_controller *ctrl)
 120 {
 121         int i;
 122         print_debug("\r\n");
 123         for(i = 0; i < 4; i++) {
 124                 unsigned device;
 125                 device = ctrl->channel0[i];
 126                 if (device) {
 127                         int j;
 128                         print_debug("dimm: ");
 129                         print_debug_hex8(i);
 130                         print_debug(".0: ");
 131                         print_debug_hex8(device);
 132                         for(j = 0; j < 256; j++) {
 133                                 int status;
 134                                 unsigned char byte;
 135                                 if ((j & 0xf) == 0) {
 136                                         print_debug("\r\n");
 137                                         print_debug_hex8(j);
 138                                         print_debug(": ");
 139                                 }
 140                                 status = smbus_read_byte(device, j);
 141                                 if (status < 0) {
 142                                         print_debug("bad device\r\n");
 143                                         break;
 144                                 }
 145                                 byte = status & 0xff;
 146                                 print_debug_hex8(byte);
 147                                 print_debug_char(' ');
 148                         }
 149                         print_debug("\r\n");
 150                 }
 151                 device = ctrl->channel1[i];
 152                 if (device) {
 153                         int j;
 154                         print_debug("dimm: ");
 155                         print_debug_hex8(i);
 156                         print_debug(".1: ");
 157                         print_debug_hex8(device);
 158                         for(j = 0; j < 256; j++) {
 159                                 int status;
 160                                 unsigned char byte;
 161                                 if ((j & 0xf) == 0) {
 162                                         print_debug("\r\n");
 163                                         print_debug_hex8(j);
 164                                         print_debug(": ");
 165                                 }
 166                                 status = smbus_read_byte(device, j);
 167                                 if (status < 0) {
 168                                         print_debug("bad device\r\n");
 169                                         break;
 170                                 }
 171                                 byte = status & 0xff;
 172                                 print_debug_hex8(byte);
 173                                 print_debug_char(' ');
 174                         }
 175                         print_debug("\r\n");
 176                 }
 177         }
 178 }
 179
 180
 181 static void main(void)
 182 {
 183         static const struct mem_controller cpu0 = {
 184                 .f0 = PCI_DEV(0, 0x18, 0),
 185                 .f1 = PCI_DEV(0, 0x18, 1),
 186                 .f2 = PCI_DEV(0, 0x18, 2),
 187                 .f3 = PCI_DEV(0, 0x18, 3),
 188                 .channel0 = { (0xa << 3), (0xa << 3)|1, 0, 0 },
 189                 .channel1 = { 0, 0, 0, 0},
 190         };
 191         uart_init();
 192         console_init();
 193 #if 0
 194         print_debug(" XIP_ROM_BASE: ");
 195         print_debug_hex32(XIP_ROM_BASE);
 196         print_debug(" XIP_ROM_SIZE: ");
 197         print_debug_hex32(XIP_ROM_SIZE);
 198         print_debug("\r\n");
 199 #endif
 200         if (boot_cpu() && !cpu_init_detected()) {
 201                 setup_default_resource_map();
 202                 setup_coherent_ht_domain();
 203                 enumerate_ht_chain();
 204                 print_pci_devices();
 205                 enable_smbus();
 206                 dump_spd_registers(&cpu0);
 207                 sdram_initialize(&cpu0);
 208
 209                 dump_pci_device(PCI_DEV(0, 0x18, 2));
 210
 211                 /* Check the first 512M */
 212                 msr_t msr;
 213                 msr = rdmsr(TOP_MEM);
 214                 print_debug("TOP_MEM: ");
 215                 print_debug_hex32(msr.hi);
 216                 print_debug_hex32(msr.lo);
 217                 print_debug("\r\n");
 218                 ram_check(0x00000000, msr.lo);
 219         }
 220 }