src/mainboard/amd/solo/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <cpu/p6/apic.h>
   6 #include <arch/io.h>
   7 #include <device/pnp.h>
   8 #include <arch/romcc_io.h>
   9 #include "pc80/serial.c"
  10 #include "arch/i386/lib/console.c"
  11 #include "ram/ramtest.c"
  12 #include "northbridge/amd/amdk8/early_ht.c"
  13 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/k8/apic_timer.c"
  16 #include "lib/delay.c"
  17 #include "cpu/p6/boot_cpu.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "debug.c"
  20 #include "northbridge/amd/amdk8/cpu_rev.c"
  21
  22 #define SIO_BASE 0x2e
  23
  24 static void memreset_setup(void)
  25 {
  26         /* Set the memreset low */
  27         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  28         /* Ensure the BIOS has control of the memory lines */
  29 }
  30
  31 static void memreset(int controllers, const struct mem_controller *ctrl)
  32 {
  33         udelay(800);
  34         /* Set memreset_high */
  35         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  36         udelay(90);
  37 }
  38
  39 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  40 {
  41         /* since the AMD Solo is a UP only machine, we can
  42          * always return the default row entry value
  43          */
  44         return 0x00010101; /* default row entry */
  45 }
  46
  47 static inline int spd_read_byte(unsigned device, unsigned address)
  48 {
  49         return smbus_read_byte(device, address);
  50 }
  51
  52 /* no specific code here. this should go away completely */
  53 static void coherent_ht_mainboard(unsigned cpus)
  54 {
  55 }
  56
  57 #include "northbridge/amd/amdk8/raminit.c"
  58 #include "northbridge/amd/amdk8/coherent_ht.c"
  59 #include "sdram/generic_sdram.c"
  60
  61 static void enable_lapic(void)
  62 {
  63
  64         msr_t msr;
  65         msr = rdmsr(0x1b);
  66         msr.hi &= 0xffffff00;
  67         msr.lo &= 0x000007ff;
  68         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
  69         wrmsr(0x1b, msr);
  70 }
  71
  72 static void stop_this_cpu(void)
  73 {
  74         unsigned apicid;
  75         apicid = apic_read(APIC_ID) >> 24;
  76
  77         /* Send an APIC INIT to myself */
  78         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
  79         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
  80         /* Wait for the ipi send to finish */
  81         apic_wait_icr_idle();
  82
  83         /* Deassert the APIC INIT */
  84         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
  85         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
  86         /* Wait for the ipi send to finish */
  87         apic_wait_icr_idle();
  88
  89         /* If I haven't halted spin forever */
  90         for(;;) {
  91                 hlt();
  92         }
  93 }
  94
  95 #define PC87360_FDC  0x00
  96 #define PC87360_PP   0x01
  97 #define PC87360_SP2  0x02
  98 #define PC87360_SP1  0x03
  99 #define PC87360_SWC  0x04
 100 #define PC87360_KBCM 0x05
 101 #define PC87360_KBCK 0x06
 102 #define PC87360_GPIO 0x07
 103 #define PC87360_ACB  0x08
 104 #define PC87360_FSCM 0x09
 105 #define PC87360_WDT  0x0A
 106
 107 /* FIXME: Do we really need this on Solo boards? */
 108 static void pc87360_enable_serial(void)
 109 {
 110         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 111         pnp_set_enable(SIO_BASE, 1);
 112         pnp_set_iobase0(SIO_BASE, 0x3f8);
 113 }
 114
 115 static void main(void)
 116 {
 117         /*
 118          * GPIO28 of 8111 will control H0_MEMRESET_L
 119          */
 120         static const struct mem_controller cpu[] = {
 121                 {
 122                         .node_id = 0,
 123                         .f0 = PCI_DEV(0, 0x18, 0),
 124                         .f1 = PCI_DEV(0, 0x18, 1),
 125                         .f2 = PCI_DEV(0, 0x18, 2),
 126                         .f3 = PCI_DEV(0, 0x18, 3),
 127                         .channel0 = { (0xa<<3), (0xa<<3)|1, 0, 0 },
 128                         .channel1 = { 0, 0, 0, 0 },
 129                 }
 130         };
 131
 132         if (cpu_init_detected()) {
 133                 asm("jmp __cpu_reset");
 134         }
 135
 136         enable_lapic();
 137         init_timer();
 138
 139 #if 0
 140         /* Enabling this will make romcc segfault - 2003/10/13 */
 141         if (!boot_cpu()) {
 142                 print_err("This LinuxBIOS image is built for UP only.\n");
 143         }
 144 #endif
 145
 146         pc87360_enable_serial();
 147
 148         uart_init();
 149         console_init();
 150         setup_default_resource_map();
 151         setup_coherent_ht_domain();
 152         enumerate_ht_chain(0);
 153         distinguish_cpu_resets(0);
 154
 155         enable_smbus();
 156
 157         memreset_setup();
 158         sdram_initialize(1, cpu);
 159
 160         msr_t msr;
 161         msr = rdmsr(TOP_MEM);
 162         print_debug("TOP_MEM: ");
 163         print_debug_hex32(msr.hi);
 164         print_debug_hex32(msr.lo);
 165         print_debug("\r\n");
 166
 167         ram_check(0x00000000, msr.lo);
 168
 169 }