src/mainboard/amd/solo/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <cpu/p6/apic.h>
   5 #include <arch/io.h>
   6 #include <device/pnp.h>
   7 #include <arch/romcc_io.h>
   8 #include "pc80/serial.c"
   9 #include "arch/i386/lib/console.c"
  10 #include "ram/ramtest.c"
  11 #include "northbridge/amd/amdk8/early_ht.c"
  12 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/k8/apic_timer.c"
  15 #include "lib/delay.c"
  16 #include "cpu/p6/boot_cpu.c"
  17 #include "northbridge/amd/amdk8/reset_test.c"
  18 #include "debug.c"
  19 #include "northbridge/amd/amdk8/cpu_rev.c"
  20
  21 #define SIO_BASE 0x2e
  22
  23 static void memreset_setup(void)
  24 {
  25         if (is_cpu_pre_c0()) {
  26                 /* Set the memreset low */
  27                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  28                 /* Ensure the BIOS has control of the memory lines */
  29                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  30         }
  31         else {
  32                 /* Ensure the CPU has controll of the memory lines */
  33                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  34         }
  35 }
  36
  37 static void memreset(int controllers, const struct mem_controller *ctrl)
  38 {
  39         if (is_cpu_pre_c0()) {
  40                 udelay(800);
  41                 /* Set memreset_high */
  42                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  43                 udelay(90);
  44         }
  45 }
  46
  47 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  48 {
  49         /* since the AMD Solo is a UP only machine, we can
  50          * always return the default row entry value
  51          */
  52         return 0x00010101; /* default row entry */
  53 }
  54
  55 static inline int spd_read_byte(unsigned device, unsigned address)
  56 {
  57         return smbus_read_byte(device, address);
  58 }
  59
  60 /* no specific code here. this should go away completely */
  61 static void coherent_ht_mainboard(unsigned cpus)
  62 {
  63 }
  64
  65 #include "northbridge/amd/amdk8/raminit.c"
  66 #include "northbridge/amd/amdk8/coherent_ht.c"
  67 #include "sdram/generic_sdram.c"
  68
  69 static void enable_lapic(void)
  70 {
  71
  72         msr_t msr;
  73         msr = rdmsr(0x1b);
  74         msr.hi &= 0xffffff00;
  75         msr.lo &= 0x000007ff;
  76         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
  77         wrmsr(0x1b, msr);
  78 }
  79
  80 static void stop_this_cpu(void)
  81 {
  82         unsigned apicid;
  83         apicid = apic_read(APIC_ID) >> 24;
  84
  85         /* Send an APIC INIT to myself */
  86         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
  87         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
  88         /* Wait for the ipi send to finish */
  89         apic_wait_icr_idle();
  90
  91         /* Deassert the APIC INIT */
  92         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
  93         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
  94         /* Wait for the ipi send to finish */
  95         apic_wait_icr_idle();
  96
  97         /* If I haven't halted spin forever */
  98         for(;;) {
  99                 hlt();
 100         }
 101 }
 102
 103 #define PC87360_FDC  0x00
 104 #define PC87360_PP   0x01
 105 #define PC87360_SP2  0x02
 106 #define PC87360_SP1  0x03
 107 #define PC87360_SWC  0x04
 108 #define PC87360_KBCM 0x05
 109 #define PC87360_KBCK 0x06
 110 #define PC87360_GPIO 0x07
 111 #define PC87360_ACB  0x08
 112 #define PC87360_FSCM 0x09
 113 #define PC87360_WDT  0x0A
 114
 115 /* FIXME: Do we really need this on Solo boards? */
 116 static void pc87360_enable_serial(void)
 117 {
 118         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 119         pnp_set_enable(SIO_BASE, 1);
 120         pnp_set_iobase0(SIO_BASE, 0x3f8);
 121 }
 122
 123 static void main(void)
 124 {
 125         static const struct mem_controller cpu[] = {
 126                 {
 127                         .node_id = 0,
 128                         .f0 = PCI_DEV(0, 0x18, 0),
 129                         .f1 = PCI_DEV(0, 0x18, 1),
 130                         .f2 = PCI_DEV(0, 0x18, 2),
 131                         .f3 = PCI_DEV(0, 0x18, 3),
 132                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, 0, 0 },
 133                         .channel1 = { 0, 0, 0, 0 },
 134                 }
 135         };
 136         if (cpu_init_detected()) {
 137                 asm("jmp __cpu_reset");
 138         }
 139         enable_lapic();
 140         init_timer();
 141
 142 #if 0
 143         /* Enabling this will make romcc segfault - 2003/10/13 */
 144         if (!boot_cpu()) {
 145                 print_err("This LinuxBIOS image is built for UP only.\n");
 146         }
 147 #endif
 148         pc87360_enable_serial();
 149         uart_init();
 150         console_init();
 151         setup_default_resource_map();
 152         setup_coherent_ht_domain();
 153         enumerate_ht_chain(0);
 154         distinguish_cpu_resets(0);
 155
 156 #if 0
 157         print_pci_devices();
 158 #endif
 159         enable_smbus();
 160 #if 0
 161         dump_spd_registers(&cpu[0]);
 162 #endif
 163         memreset_setup();
 164         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 165
 166 #if 0
 167         dump_pci_devices();
 168 #endif
 169 #if 0
 170         dump_pci_device(PCI_DEV(0, 0x18, 2));
 171 #endif
 172
 173         /* Check all of memory */
 174 #if 0
 175         msr_t msr;
 176         msr = rdmsr(TOP_MEM);
 177         print_debug("TOP_MEM: ");
 178         print_debug_hex32(msr.hi);
 179         print_debug_hex32(msr.lo);
 180         print_debug("\r\n");
 181 #endif
 182 #if 0
 183         ram_check(0x00000000, msr.lo);
 184 #endif
 185 #if 0
 186         static const struct {
 187                 unsigned long lo, hi;
 188         } check_addrs[] = {
 189                 /* Check 16MB of memory @ 0*/
 190                 { 0x00000000, 0x01000000 },
 191         };
 192         int i;
 193         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 194                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 195         }
 196 #endif
 197 }