3 #include <device/pci_def.h>
4 #include <cpu/p6/apic.h>
6 #include <device/pnp.h>
7 #include <arch/romcc_io.h>
8 #include "pc80/serial.c"
9 #include "arch/i386/lib/console.c"
10 #include "ram/ramtest.c"
11 #include "northbridge/amd/amdk8/early_ht.c"
12 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
13 #include "northbridge/amd/amdk8/raminit.h"
14 #include "cpu/k8/apic_timer.c"
15 #include "lib/delay.c"
16 #include "cpu/p6/boot_cpu.c"
17 #include "northbridge/amd/amdk8/reset_test.c"
19 #include "northbridge/amd/amdk8/cpu_rev.c"
23 static void memreset_setup(void)
25 if (is_cpu_pre_c0()) {
26 /* Set the memreset low */
27 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
28 /* Ensure the BIOS has control of the memory lines */
29 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
32 /* Ensure the CPU has controll of the memory lines */
33 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
37 static void memreset(int controllers, const struct mem_controller *ctrl)
39 if (is_cpu_pre_c0()) {
41 /* Set memreset_high */
42 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
47 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
49 /* since the AMD Solo is a UP only machine, we can
50 * always return the default row entry value
52 return 0x00010101; /* default row entry */
55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
60 static inline int spd_read_byte(unsigned device, unsigned address)
62 return smbus_read_byte(device, address);
65 /* no specific code here. this should go away completely */
66 static void coherent_ht_mainboard(unsigned cpus)
70 #include "northbridge/amd/amdk8/raminit.c"
71 #include "northbridge/amd/amdk8/coherent_ht.c"
72 #include "sdram/generic_sdram.c"
74 static void enable_lapic(void)
81 msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
85 static void stop_this_cpu(void)
88 apicid = apic_read(APIC_ID) >> 24;
90 /* Send an APIC INIT to myself */
91 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
92 apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
93 /* Wait for the ipi send to finish */
96 /* Deassert the APIC INIT */
97 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
98 apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
99 /* Wait for the ipi send to finish */
100 apic_wait_icr_idle();
102 /* If I haven't halted spin forever */
108 #define PC87360_FDC 0x00
109 #define PC87360_PP 0x01
110 #define PC87360_SP2 0x02
111 #define PC87360_SP1 0x03
112 #define PC87360_SWC 0x04
113 #define PC87360_KBCM 0x05
114 #define PC87360_KBCK 0x06
115 #define PC87360_GPIO 0x07
116 #define PC87360_ACB 0x08
117 #define PC87360_FSCM 0x09
118 #define PC87360_WDT 0x0A
120 /* FIXME: Do we really need this on Solo boards? */
121 static void pc87360_enable_serial(void)
123 pnp_set_logical_device(SIO_BASE, PC87360_SP1);
124 pnp_set_enable(SIO_BASE, 1);
125 pnp_set_iobase0(SIO_BASE, 0x3f8);
128 static void main(void)
130 static const struct mem_controller cpu[] = {
133 .f0 = PCI_DEV(0, 0x18, 0),
134 .f1 = PCI_DEV(0, 0x18, 1),
135 .f2 = PCI_DEV(0, 0x18, 2),
136 .f3 = PCI_DEV(0, 0x18, 3),
137 .channel0 = { (0xa<<3)|0, (0xa<<3)|1, 0, 0 },
138 .channel1 = { 0, 0, 0, 0 },
141 if (cpu_init_detected()) {
142 asm("jmp __cpu_reset");
148 /* Enabling this will make romcc segfault - 2003/10/13 */
150 print_err("This LinuxBIOS image is built for UP only.\n");
153 pc87360_enable_serial();
156 setup_default_resource_map();
157 setup_coherent_ht_domain();
158 enumerate_ht_chain(0);
159 distinguish_cpu_resets(0);
166 dump_spd_registers(&cpu[0]);
169 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
175 dump_pci_device(PCI_DEV(0, 0x18, 2));
178 /* Check all of memory */
181 msr = rdmsr(TOP_MEM);
182 print_debug("TOP_MEM: ");
183 print_debug_hex32(msr.hi);
184 print_debug_hex32(msr.lo);
188 ram_check(0x00000000, msr.lo);
191 static const struct {
192 unsigned long lo, hi;
194 /* Check 16MB of memory @ 0*/
195 { 0x00000000, 0x01000000 },
198 for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
199 ram_check(check_addrs[i].lo, check_addrs[i].hi);