src/mainboard/amd/solo/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp.h>
   6 #include <arch/romcc_io.h>
   7 #include <arch/smp/lapic.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "ram/ramtest.c"
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/k8/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/p6/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "debug.c"
  21 #include "northbridge/amd/amdk8/cpu_rev.c"
  22 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  23
  24 #define SIO_BASE 0x2e
  25
  26 static void hard_reset(void)
  27 {
  28         set_bios_reset();
  29
  30         /* enable cf9 */
  31         pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1);
  32         /* reset */
  33         outb(0x0e, 0x0cf9);
  34 }
  35
  36 static void soft_reset(void)
  37 {
  38         set_bios_reset();
  39         pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1);
  40 }
  41
  42 static void memreset_setup(void)
  43 {
  44         if (is_cpu_pre_c0()) {
  45                 /* Set the memreset low */
  46                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  47                 /* Ensure the BIOS has control of the memory lines */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  49         }
  50         else {
  51                 /* Ensure the CPU has controll of the memory lines */
  52                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  53         }
  54 }
  55
  56 static void memreset(int controllers, const struct mem_controller *ctrl)
  57 {
  58         if (is_cpu_pre_c0()) {
  59                 udelay(800);
  60                 /* Set memreset_high */
  61                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  62                 udelay(90);
  63         }
  64 }
  65
  66 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  67 {
  68         /* since the AMD Solo is a UP only machine, we can
  69          * always return the default row entry value
  70          */
  71         return 0x00010101; /* default row entry */
  72 }
  73
  74 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  75 {
  76         /* nothing to do */
  77 }
  78
  79 static inline int spd_read_byte(unsigned device, unsigned address)
  80 {
  81         return smbus_read_byte(device, address);
  82 }
  83
  84
  85 #include "northbridge/amd/amdk8/raminit.c"
  86 #include "northbridge/amd/amdk8/coherent_ht.c"
  87 #include "sdram/generic_sdram.c"
  88
  89 static void main(void)
  90 {
  91         static const struct mem_controller cpu[] = {
  92                 {
  93                         .node_id = 0,
  94                         .f0 = PCI_DEV(0, 0x18, 0),
  95                         .f1 = PCI_DEV(0, 0x18, 1),
  96                         .f2 = PCI_DEV(0, 0x18, 2),
  97                         .f3 = PCI_DEV(0, 0x18, 3),
  98                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, 0, 0 },
  99                         .channel1 = { 0, 0, 0, 0 },
 100                 }
 101         };
 102         int needs_reset;
 103         enable_lapic();
 104         init_timer();
 105         if (cpu_init_detected()) {
 106                 asm("jmp __cpu_reset");
 107         }
 108         enable_lapic();
 109         init_timer();
 110         distinguish_cpu_resets();
 111         if (!boot_cpu()) {
 112                 print_err("This LinuxBIOS image is built for UP only.\n");
 113                 stop_this_cpu();
 114         }
 115         pc87360_enable_serial(SIO_BASE, TTYS0_BASE);
 116         uart_init();
 117         console_init();
 118         setup_default_resource_map();
 119         needs_reset = setup_coherent_ht_domain();
 120         needs_reset = ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 121         if (needs_reset) {
 122                 print_info("ht reset -");
 123                 soft_reset();
 124         }
 125 #if 0
 126         print_pci_devices();
 127 #endif
 128         enable_smbus();
 129 #if 0
 130         dump_spd_registers(&cpu[0]);
 131 #endif
 132         memreset_setup();
 133         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 134
 135 #if 0
 136         dump_pci_devices();
 137 #endif
 138 #if 0
 139         dump_pci_device(PCI_DEV(0, 0x18, 2));
 140 #endif
 141
 142         /* Check all of memory */
 143 #if 0
 144         msr_t msr;
 145         msr = rdmsr(TOP_MEM);
 146         print_debug("TOP_MEM: ");
 147         print_debug_hex32(msr.hi);
 148         print_debug_hex32(msr.lo);
 149         print_debug("\r\n");
 150 #endif
 151 #if 0
 152         ram_check(0x00000000, msr.lo);
 153 #endif
 154 #if 0
 155         static const struct {
 156                 unsigned long lo, hi;
 157         } check_addrs[] = {
 158                 /* Check 16MB of memory @ 0*/
 159                 { 0x00000000, 0x01000000 },
 160         };
 161         int i;
 162         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 163                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 164         }
 165 #endif
 166 }