4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
9 uses HARD_RESET_FUNCTION
11 uses HAVE_OPTION_TABLE
20 uses ROM_SECTION_OFFSET
21 uses CONFIG_ROM_STREAM
22 uses CONFIG_ROM_STREAM_START
30 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
36 uses LINUXBIOS_EXTRA_VERSION
41 uses DEFAULT_CONSOLE_LOGLEVEL
42 uses MAXIMUM_CONSOLE_LOGLEVEL
43 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
56 ## ROM_SIZE is the size of boot ROM that this board will use.
58 default ROM_SIZE=524288
61 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
63 default FALLBACK_SIZE=131072
66 ## Build code for the fallback boot
68 default HAVE_FALLBACK_BOOT=1
71 ## Build code to reset the motherboard from linuxBIOS
73 default HAVE_HARD_RESET=1
76 ## Funky hard reset implementation
78 default HARD_RESET_BUS=1
79 default HARD_RESET_DEVICE=4
80 default HARD_RESET_FUNCTION=0
83 ## Build code to export a programmable irq routing table
85 default HAVE_PIRQ_TABLE=1
86 default IRQ_SLOT_COUNT=9
89 ## Build code to export an x86 MP table
90 ## Useful for specifying IRQ routing values
92 default HAVE_MP_TABLE=1
95 ## Build code to export a CMOS option table
97 default HAVE_OPTION_TABLE=1
100 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
102 default LB_CKS_RANGE_START=49
103 default LB_CKS_RANGE_END=122
104 default LB_CKS_LOC=123
107 ## Build code for SMP support
108 ## Only worry about 2 micro processors
111 default CONFIG_MAX_CPUS=1
114 ## Build code to setup a generic IOAPIC
116 default CONFIG_IOAPIC=1
119 ## Clean up the motherboard id strings
121 default MAINBOARD_PART_NUMBER="SOLO"
122 default MAINBOARD_VENDOR="AMD"
125 ### LinuxBIOS layout values
128 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
129 default ROM_IMAGE_SIZE = 65536
132 ## Use a small 8K stack
134 default STACK_SIZE=0x2000
137 ## Use a small 16K heap
139 default HEAP_SIZE=0x4000
142 ## Only use the option table in a normal image
144 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
147 ## LinuxBIOS C code runs at this location in RAM
149 default _RAMBASE=0x00004000
152 ## Load the payload from the ROM
154 default CONFIG_ROM_STREAM = 1
157 ### Defaults of options that you may want to override in the target config file
161 ## The default compiler
163 default CROSS_COMPILE=""
164 default CC="$(CROSS_COMPILE)gcc -m32"
168 ## The Serial Console
171 # To Enable the Serial Console
172 default CONFIG_CONSOLE_SERIAL8250=1
174 ## Select the serial console baud rate
175 default TTYS0_BAUD=115200
176 #default TTYS0_BAUD=57600
177 #default TTYS0_BAUD=38400
178 #default TTYS0_BAUD=19200
179 #default TTYS0_BAUD=9600
180 #default TTYS0_BAUD=4800
181 #default TTYS0_BAUD=2400
182 #default TTYS0_BAUD=1200
184 # Select the serial console base port
185 default TTYS0_BASE=0x3f8
187 # Select the serial protocol
188 # This defaults to 8 data bits, 1 stop bit, and no parity
189 default TTYS0_LCS=0x3
192 ### Select the linuxBIOS loglevel
194 ## EMERG 1 system is unusable
195 ## ALERT 2 action must be taken immediately
196 ## CRIT 3 critical conditions
197 ## ERR 4 error conditions
198 ## WARNING 5 warning conditions
199 ## NOTICE 6 normal but significant condition
200 ## INFO 7 informational
201 ## DEBUG 8 debug-level messages
202 ## SPEW 9 Way too many details
204 ## Request this level of debugging output
205 default DEFAULT_CONSOLE_LOGLEVEL=8
206 ## At a maximum only compile in this level of debugging
207 default MAXIMUM_CONSOLE_LOGLEVEL=8
210 ## Select power on after power fail setting
211 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"