3 uses USE_FALLBACK_IMAGE
11 uses ROM_SECTION_OFFSET
12 uses CONFIG_ROM_STREAM_START
18 ## ROM_SIZE is the size of boot ROM that this board will use.
19 default ROM_SIZE 524288
26 ## Build code for the fallback boot
28 option HAVE_FALLBACK_BOOT=1
31 ## Build code to reset the motherboard from linuxBIOS
33 option HAVE_HARD_RESET=0
36 ## Build code to export a programmable irq routing table
38 option HAVE_PIRQ_TABLE=1
39 option IRQ_SLOT_COUNT=7
42 ## Build code to export an x86 MP table
43 ## Useful for specifying IRQ routing values
45 option HAVE_MP_TABLE=1
48 ## Build code to export a CMOS option table
50 option HAVE_OPTION_TABLE=1
53 ## AMD Solo is a 1cpu board
56 option CONFIG_MAX_CPUS=1
59 ## Build code to setup a generic IOAPIC
61 option CONFIG_IOAPIC=1
64 ## Clean up the motherboard id strings
66 option MAINBOARD_PART_NUMBER="SOLO7"
67 option MAINBOARD_VENDOR="AMD"
70 ### LinuxBIOS layout values
73 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
74 option ROM_IMAGE_SIZE = 65536
77 ## Use a small 8K stack
79 option STACK_SIZE=0x2000
82 ## Use a small 16K heap
84 option HEAP_SIZE=0x4000
87 ## Only use the option table in a normal image
89 option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
92 ## Compute the location and size of where this firmware image
93 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
96 option ROM_SECTION_SIZE = FALLBACK_SIZE
97 option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
99 option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
100 option ROM_SECTION_OFFSET = 0
104 ## Compute the start location and size size of
105 ## The linuxBIOS bootloader.
107 option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
108 option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
109 option CONFIG_ROM_STREAM = 1
112 ## Compute where this copy of linuxBIOS will start in the boot rom
114 option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
117 ## Compute a range of ROM that can cached to speed up linuxBIOS,
120 ## XIP_ROM_SIZE must be a power of 2.
121 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
123 option XIP_ROM_SIZE=65536
124 option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
127 ## Set all of the defaults for an x86 architecture
134 ## Build the objects we have code for in this directory.
139 #object static_devices.o
140 if HAVE_MP_TABLE object mptable.o end
141 if HAVE_PIRQ_TABLE object irq_tables.o end
147 makerule ./failover.E
148 depends "$(MAINBOARD)/failover.c"
149 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
152 makerule ./failover.inc
153 depends "./failover.E ./romcc"
154 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
158 depends "$(MAINBOARD)/auto.c"
159 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
162 depends "./auto.E ./romcc"
163 action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
167 ## Build our 16 bit and 32 bit linuxBIOS entry code
169 mainboardinit cpu/i386/entry16.inc
170 mainboardinit cpu/i386/entry32.inc
171 ldscript /cpu/i386/entry16.lds
172 ldscript /cpu/i386/entry32.lds
175 ## Build our reset vector (This is where linuxBIOS is entered)
177 if USE_FALLBACK_IMAGE
178 mainboardinit cpu/i386/reset16.inc
179 ldscript /cpu/i386/reset16.lds
181 mainboardinit cpu/i386/reset32.inc
182 ldscript /cpu/i386/reset32.lds
185 ### Should this be in the northbridge code?
186 mainboardinit arch/i386/lib/cpu_reset.inc
189 ## Include an id string (For safe flashing)
191 mainboardinit arch/i386/lib/id.inc
192 ldscript /arch/i386/lib/id.lds
197 mainboardinit cpu/k8/earlymtrr.inc
200 ### This is the early phase of linuxBIOS startup
201 ### Things are delicate and we test to see if we should
202 ### failover to another image.
204 if USE_FALLBACK_IMAGE
205 ldscript /arch/i386/lib/failover.lds
206 mainboardinit ./failover.inc
210 ### O.k. We aren't just an intermediary anymore!
216 mainboardinit cpu/k8/enable_mmx_sse.inc
217 mainboardinit ./auto.inc
218 mainboardinit cpu/k8/disable_mmx_sse.inc
221 ## Include the secondary Configuration files
226 northbridge amd/amdk8 "mc0"
233 southbridge amd/amd8111 "amd8111"
253 register "com1" = "{1, 0, 0x3f8, 4}"
254 register "lpt" = "{1}"
257 southbridge amd/amd8151 "amd8151"
264 register "up" = "{ .chip = &amd8111, .ht_width=16, .ht_speed=600 }"
268 ## Include the old serial code for those few places that still need it.
270 mainboardinit pc80/serial.inc
271 mainboardinit arch/i386/lib/console.inc