3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
16 uses ROM_SECTION_OFFSET
17 uses CONFIG_ROM_STREAM
18 uses CONFIG_ROM_STREAM_START
26 uses LB_CKS_RANGE_START
29 uses MAINBOARD_PART_NUMBER
33 ## ROM_SIZE is the size of boot ROM that this board will use.
34 default ROM_SIZE=262144
41 ## Build code for the fallback boot
43 default HAVE_FALLBACK_BOOT=1
46 ## Build code to reset the motherboard from linuxBIOS
48 default HAVE_HARD_RESET=1
51 ## Build code to export a programmable irq routing table
53 default HAVE_PIRQ_TABLE=1
54 default IRQ_SLOT_COUNT=8
57 ## Build code to export an x86 MP table
58 ## Useful for specifying IRQ routing values
60 default HAVE_MP_TABLE=1
63 ## Build code to export a CMOS option table
65 default HAVE_OPTION_TABLE=1
68 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
70 default LB_CKS_RANGE_START=49
71 default LB_CKS_RANGE_END=122
72 default LB_CKS_LOC=123
75 ## AMD Solo is a 1cpu board
78 default CONFIG_MAX_CPUS=1
81 ## Build code to setup a generic IOAPIC
83 default CONFIG_IOAPIC=1
86 ## Clean up the motherboard id strings
88 #default MAINBOARD_PART_NUMBER="SOLO7"
89 #default MAINBOARD_VENDOR="AMD"
92 ### LinuxBIOS layout values
95 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
96 default ROM_IMAGE_SIZE = 65536
99 ## Use a small 8K stack
101 default STACK_SIZE=0x2000
104 ## Use a small 16K heap
106 default HEAP_SIZE=0x4000
109 ## Only use the option table in a normal image
111 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
114 ## Compute the location and size of where this firmware image
115 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
117 if USE_FALLBACK_IMAGE
118 default ROM_SECTION_SIZE = FALLBACK_SIZE
119 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
121 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
122 default ROM_SECTION_OFFSET = 0
126 ## Compute the start location and size size of
127 ## The linuxBIOS bootloader.
129 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
130 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
131 default CONFIG_ROM_STREAM = 1
134 ## Compute where this copy of linuxBIOS will start in the boot rom
136 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
139 ## Compute a range of ROM that can cached to speed up linuxBIOS,
142 ## XIP_ROM_SIZE must be a power of 2.
143 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
145 default XIP_ROM_SIZE=65536
146 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
149 ## Set all of the defaults for an x86 architecture
156 ## Build the objects we have code for in this directory.
160 if HAVE_MP_TABLE object mptable.o end
161 if HAVE_PIRQ_TABLE object irq_tables.o end
167 makerule ./failover.E
168 depends "$(MAINBOARD)/failover.c"
169 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
172 makerule ./failover.inc
173 depends "./failover.E ./romcc"
174 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
178 depends "$(MAINBOARD)/auto.c option_table.h "
179 action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
182 depends "./auto.E ./romcc"
183 action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
187 ## Build our 16 bit and 32 bit linuxBIOS entry code
189 mainboardinit cpu/i386/entry16.inc
190 mainboardinit cpu/i386/entry32.inc
191 #mainboardinit cpu/i386/bist32.inc
192 ldscript /cpu/i386/entry16.lds
193 ldscript /cpu/i386/entry32.lds
196 ## Build our reset vector (This is where linuxBIOS is entered)
198 if USE_FALLBACK_IMAGE
199 mainboardinit cpu/i386/reset16.inc
200 ldscript /cpu/i386/reset16.lds
202 mainboardinit cpu/i386/reset32.inc
203 ldscript /cpu/i386/reset32.lds
206 ### Should this be in the northbridge code?
207 mainboardinit arch/i386/lib/cpu_reset.inc
210 ## Include an id string (For safe flashing)
212 mainboardinit arch/i386/lib/id.inc
213 ldscript /arch/i386/lib/id.lds
218 mainboardinit cpu/k8/earlymtrr.inc
221 ### This is the early phase of linuxBIOS startup
222 ### Things are delicate and we test to see if we should
223 ### failover to another image.
225 if USE_FALLBACK_IMAGE
226 ldscript /arch/i386/lib/failover.lds
227 mainboardinit ./failover.inc
231 ### O.k. We aren't just an intermediary anymore!
237 mainboardinit cpu/k8/enable_mmx_sse.inc
238 mainboardinit ./auto.inc
239 mainboardinit cpu/k8/disable_mmx_sse.inc
242 ## Include the secondary Configuration files
247 northbridge amd/amdk8 "mc0"
254 southbridge amd/amd8151 "amd8151" link 0
258 southbridge amd/amd8111 "amd8111" link 0
270 superio NSC/pc87360 link 1
271 pnp 2e.0 off # Floppy
275 pnp 2e.1 off # Parallel Port
286 pnp 2e.6 on # Keyboard
302 ## Include the old serial code for those few places that still need it.
304 mainboardinit pc80/serial.inc
305 mainboardinit arch/i386/lib/console.inc
306 #mainboardinit cpu/i386/bist32_fail.inc