src/mainboard/amd/solo/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44 #object reset.o
  45
  46 ##
  47 ## Romcc output
  48 ##
  49 makerule ./failover.E
  50         depends "$(MAINBOARD)/failover.c"
  51         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
  52 end
  53
  54 makerule ./failover.inc
  55         depends "./failover.E ./romcc"
  56         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
  57 end
  58
  59 makerule ./auto.E
  60         depends "$(MAINBOARD)/auto.c option_table.h "
  61         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
  62 end
  63 makerule ./auto.inc
  64         depends "./auto.E ./romcc"
  65         action  "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
  66 end
  67
  68 ##
  69 ## Build our 16 bit and 32 bit linuxBIOS entry code
  70 ##
  71 mainboardinit cpu/x86/16bit/entry16.inc
  72 mainboardinit cpu/x86/32bit/entry32.inc
  73 ldscript /cpu/x86/16bit/entry16.lds
  74 ldscript /cpu/x86/32bit/entry32.lds
  75
  76 ##
  77 ## Build our reset vector (This is where linuxBIOS is entered)
  78 ##
  79 if USE_FALLBACK_IMAGE
  80         mainboardinit cpu/x86/16bit/reset16.inc
  81         ldscript /cpu/x86/16bit/reset16.lds
  82 else
  83         mainboardinit cpu/x86/32bit/reset32.inc
  84         ldscript /cpu/x86/32bit/reset32.lds
  85 end
  86
  87 ### Should this be in the northbridge code?
  88 mainboardinit arch/i386/lib/cpu_reset.inc
  89
  90 ##
  91 ## Include an id string (For safe flashing)
  92 ##
  93 mainboardinit arch/i386/lib/id.inc
  94 ldscript /arch/i386/lib/id.lds
  95
  96 ###
  97 ### This is the early phase of linuxBIOS startup
  98 ### Things are delicate and we test to see if we should
  99 ### failover to another image.
 100 ###
 101 if USE_FALLBACK_IMAGE
 102         ldscript /arch/i386/lib/failover.lds
 103         mainboardinit ./failover.inc
 104 end
 105
 106 ###
 107 ### O.k. We aren't just an intermediary anymore!
 108 ###
 109
 110 ##
 111 ## Setup RAM
 112 ##
 113 mainboardinit cpu/x86/fpu/enable_fpu.inc
 114 mainboardinit cpu/x86/mmx/enable_mmx.inc
 115 mainboardinit cpu/x86/sse/enable_sse.inc
 116 mainboardinit ./auto.inc
 117 mainboardinit cpu/x86/sse/disable_sse.inc
 118 mainboardinit cpu/x86/mmx/disable_mmx.inc
 119
 120 ##
 121 ## Include the secondary Configuration files
 122 ##
 123 dir /pc80
 124 config chip.h
 125
 126 # sample config for arima/hdama
 127 chip northbridge/amd/amdk8
 128         device pci_domain 0 on
 129                 device pci 18.0 on #  northbridge
 130                         #  devices on link 0, link 0 == LDT 0
 131                         chip southbridge/amd/amd8151
 132                                 # the on/off keyword is mandatory
 133                                 device pci 0.0 on end
 134                                 device pci 1.0 on end
 135                         end
 136                         chip southbridge/amd/amd8111
 137                                 # this "device pci 0.0" is the parent the next one
 138                                 # PCI bridge
 139                                 device pci 0.0 on
 140                                         device pci 0.0 on end
 141                                         device pci 0.1 on end
 142                                         device pci 0.2 on end
 143                                         device pci 1.0 off end
 144                                 end
 145                                 device pci 1.0 on
 146                                         chip superio/NSC/pc87360
 147                                                 device  pnp 2e.0 off  # Floppy
 148                                                          io 0x60 = 0x3f0
 149                                                         irq 0x70 = 6
 150                                                         drq 0x74 = 2
 151                                                 end
 152                                                 device pnp 2e.1 off  # Parallel Port
 153                                                          io 0x60 = 0x378
 154                                                         irq 0x70 = 7
 155                                                 end
 156                                                 device pnp 2e.2 off # Com 2
 157                                                          io 0x60 = 0x2f8
 158                                                         irq 0x70 = 3
 159                                                 end
 160                                                 device pnp 2e.3 on  # Com 1
 161                                                          io 0x60 = 0x3f8
 162                                                         irq 0x70 = 4
 163                                                 end
 164                                                 device pnp 2e.4 off end # SWC
 165                                                 device pnp 2e.5 off end # Mouse
 166                                                 device pnp 2e.6 on  # Keyboard
 167                                                          io 0x60 = 0x60
 168                                                          io 0x62 = 0x64
 169                                                         irq 0x70 = 1
 170                                                 end
 171                                                 device pnp 2e.7 off end # GPIO
 172                                                 device pnp 2e.8 off end # ACB
 173                                                 device pnp 2e.9 off end # FSCM
 174                                                 device pnp 2e.a off end # WDT
 175                                         end
 176                                 end
 177                                 device pci 1.1 on end
 178                                 device pci 1.2 on end
 179                                 device pci 1.3 on
 180                                         chip drivers/generic/generic
 181                                                 #phillips pca9545 smbus mux
 182                                                 device i2c 70 on
 183                                                         # analog_devices adm1026
 184                                                         chip drivers/generic/generic
 185                                                                 device i2c 2c on end
 186                                                         end
 187                                                 end
 188                                                 device i2c 70 on end
 189                                                 device i2c 70 on end
 190                                                 device i2c 70 on end
 191                                         end
 192                                         chip drivers/generic/generic #dimm 0-0-0
 193                                                 device i2c 50 on end
 194                                         end
 195                                         chip drivers/generic/generic #dimm 0-0-1
 196                                                 device i2c 51 on end
 197                                         end
 198                                 end
 199                                 device pci 1.5 off end
 200                                 device pci 1.6 on end
 201                         end
 202                 end #  device pci 18.0
 203
 204                 device pci 18.0 on end # LDT1
 205                 device pci 18.0 on end # LDT2
 206                 device pci 18.1 on end
 207                 device pci 18.2 on end
 208                 device pci 18.3 on end
 209         end
 210         device apic_cluster 0 on
 211                 chip cpu/amd/socket_754
 212                         device apic 0 on end
 213                 end
 214         end
 215 end
 216