src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define RAMINIT_SYSINFO 0
   5
   6 #if CONFIG_LOGICAL_CPUS==1
   7         #define SET_NB_CFG_54 1
   8 #endif
   9
  10 //use by raminit
  11 #define K8_4RANK_DIMM_SUPPORT 1
  12
  13 //use bu init_cpus
  14 #if 0
  15         #define ENABLE_APIC_EXT_ID 1
  16         #define APIC_ID_OFFSET 0x10
  17         #define LIFT_BSP_APIC_ID 0
  18 #else
  19         #define ENABLE_APIC_EXT_ID 0
  20 #endif
  21
  22 //used by incoherent_ht
  23 //#define K8_SCAN_PCI_BUS 1
  24 //#define K8_ALLOCATE_IO_RANGE 1
  25
  26 #include <stdint.h>
  27 #include <device/pci_def.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include "option_table.h"
  33 #include "pc80/mc146818rtc_early.c"
  34 #include "pc80/serial.c"
  35 #include "arch/i386/lib/console.c"
  36 #include "ram/ramtest.c"
  37
  38 #if 0
  39 static void post_code(uint8_t value) {
  40 #if 1
  41         int i;
  42         for(i=0;i<0x80000;i++) {
  43                 outb(value, 0x80);
  44         }
  45 #endif
  46 }
  47 #endif
  48
  49 #include <cpu/amd/model_fxx_rev.h>
  50 #include "northbridge/amd/amdk8/incoherent_ht.c"
  51 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  52 #include "northbridge/amd/amdk8/raminit.h"
  53 #include "cpu/amd/model_fxx/apic_timer.c"
  54 #include "lib/delay.c"
  55
  56 #if CONFIG_USE_INIT == 0
  57 #include "lib/memcpy.c"
  58 #endif
  59
  60 #include "cpu/x86/lapic/boot_cpu.c"
  61 #include "northbridge/amd/amdk8/reset_test.c"
  62 #include "northbridge/amd/amdk8/debug.c"
  63 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  64
  65 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  66 #include "cpu/x86/bist.h"
  67
  68 #include "northbridge/amd/amdk8/setup_resource_map.c"
  69
  70 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  71
  72 static void hard_reset(void)
  73 {
  74         device_t dev;
  75         unsigned sblnk = get_sblnk();
  76
  77         /* Find the device */
  78 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
  79         dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 3);
  80 #else
  81         dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 3);
  82 #endif
  83
  84         set_bios_reset();
  85
  86         /* enable cf9 */
  87         pci_write_config8(dev, 0x41, 0xf1);
  88         /* reset */
  89         outb(0x0e, 0x0cf9);
  90 }
  91 static void soft_reset(void)
  92 {
  93         device_t dev;
  94         unsigned sblnk = get_sblnk();
  95
  96         /* Find the device */
  97 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
  98         dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 0);
  99 #else
 100         dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 0);
 101 #endif
 102
 103         set_bios_reset();
 104         pci_write_config8(dev, 0x47, 1);
 105 }
 106
 107 static void memreset_setup(void)
 108 {
 109    if (is_cpu_pre_c0()) {
 110         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
 111    }
 112    else {
 113         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
 114    }
 115         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 116 }
 117
 118 static void memreset(int controllers, const struct mem_controller *ctrl)
 119 {
 120    if (is_cpu_pre_c0()) {
 121         udelay(800);
 122         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
 123         udelay(90);
 124    }
 125 }
 126
 127 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 128 {
 129 #define SMBUS_HUB 0x18
 130         int ret,i;
 131         unsigned device=(ctrl->channel0[0])>>8;
 132         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
 133         i=2;
 134         do {
 135                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 136         } while ((ret!=0) && (i-->0));
 137
 138         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 139 }
 140 #if 0
 141 static inline void change_i2c_mux(unsigned device)
 142 {
 143 #define SMBUS_HUB 0x18
 144         int ret, i;
 145         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
 146         i=2;
 147         do {
 148                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 149                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
 150         } while ((ret!=0) && (i-->0));
 151         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
 152         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
 153 }
 154 #endif
 155
 156 static inline int spd_read_byte(unsigned device, unsigned address)
 157 {
 158         return smbus_read_byte(device, address);
 159 }
 160
 161
 162 #include "northbridge/amd/amdk8/raminit.c"
 163 #include "northbridge/amd/amdk8/coherent_ht.c"
 164 #include "sdram/generic_sdram.c"
 165
 166  /* tyan does not want the default */
 167 #include "resourcemap.c"
 168
 169 #include "cpu/amd/dualcore/dualcore.c"
 170
 171 #define RC0 ((1<<0)<<8)
 172 #define RC1 ((1<<1)<<8)
 173
 174 #define DIMM0 0x50
 175 #define DIMM1 0x51
 176
 177 #include "cpu/amd/car/copy_and_run.c"
 178 #include "cpu/amd/car/post_cache_as_ram.c"
 179
 180 #include "cpu/amd/model_fxx/init_cpus.c"
 181
 182 #if USE_FALLBACK_IMAGE == 1
 183
 184 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 185 #include "northbridge/amd/amdk8/early_ht.c"
 186
 187 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 188 {
 189         unsigned last_boot_normal_x = last_boot_normal();
 190
 191         /* Is this a cpu only reset? or Is this a secondary cpu? */
 192         if ((cpu_init_detectedx) || (!boot_cpu())) {
 193                 if (last_boot_normal_x) {
 194                         goto normal_image;
 195                 } else {
 196                         goto fallback_image;
 197                 }
 198         }
 199
 200         /* Nothing special needs to be done to find bus 0 */
 201         /* Allow the HT devices to be found */
 202
 203         enumerate_ht_chain();
 204
 205         /* Setup the flash access */
 206         amd8111_enable_rom();
 207
 208         /* Is this a deliberate reset by the bios */
 209 //        post_code(0x22);
 210         if (bios_reset_detected() && last_boot_normal_x) {
 211                 goto normal_image;
 212         }
 213         /* This is the primary cpu how should I boot? */
 214         else if (do_normal_boot()) {
 215                 goto normal_image;
 216         }
 217         else {
 218                 goto fallback_image;
 219         }
 220  normal_image:
 221 //        post_code(0x23);
 222         __asm__ volatile ("jmp __normal_image"
 223                 : /* outputs */
 224                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 225                 );
 226
 227  fallback_image:
 228 //        post_code(0x25);
 229         ;
 230 }
 231 #endif
 232
 233 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 234
 235 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 236 {
 237
 238 #if USE_FALLBACK_IMAGE == 1
 239         failover_process(bist, cpu_init_detectedx);
 240 #endif
 241         real_main(bist, cpu_init_detectedx);
 242
 243 }
 244
 245 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 246 {
 247         static const uint16_t spd_addr [] = {
 248                         RC0|DIMM0, 0, 0, 0,
 249                         RC0|DIMM1, 0, 0, 0,
 250 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 251                         RC1|DIMM0, 0 , 0, 0,
 252                         RC1|DIMM1, 0 , 0, 0,
 253 #endif
 254         };
 255
 256         int needs_reset;
 257         unsigned cpu_reset = 0;
 258         unsigned bsp_apicid = 0;
 259
 260         struct mem_controller ctrl[8];
 261         unsigned nodes;
 262
 263         if (bist == 0) {
 264                 bsp_apicid = init_cpus(cpu_init_detectedx);
 265         }
 266
 267 //      post_code(0x32);
 268
 269         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 270         uart_init();
 271         console_init();
 272
 273 //      dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
 274
 275         /* Halt if there was a built in self test failure */
 276         report_bist_failure(bist);
 277
 278         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 279
 280         setup_serengeti_leopard_resource_map();
 281 #if 0
 282         dump_pci_device(PCI_DEV(0, 0x18, 0));
 283         dump_pci_device(PCI_DEV(0, 0x19, 0));
 284 #endif
 285
 286         needs_reset = setup_coherent_ht_domain();
 287
 288 #if CONFIG_LOGICAL_CPUS==1
 289         // It is said that we should start core1 after all core0 launched
 290         wait_all_core0_started();
 291         start_other_cores();
 292 #endif
 293         wait_all_aps_started(bsp_apicid);
 294
 295         needs_reset |= ht_setup_chains_x();
 296
 297         if (needs_reset) {
 298                 print_info("ht reset -\r\n");
 299                 soft_reset();
 300         }
 301
 302         allow_all_aps_stop(bsp_apicid);
 303
 304         nodes = get_nodes();
 305         //It's the time to set ctrl now;
 306         fill_mem_ctrl(nodes, ctrl, spd_addr);
 307
 308         enable_smbus();
 309 #if 0
 310         dump_spd_registers(&cpu[0]);
 311 #endif
 312 #if 0
 313         dump_smbus_registers();
 314 #endif
 315
 316         memreset_setup();
 317
 318 //      init_timer(); // Need to use TMICT to synconize FID/VID
 319
 320         sdram_initialize(nodes, ctrl);
 321
 322 #if 0
 323         print_pci_devices();
 324 #endif
 325
 326 #if 0
 327         dump_pci_devices();
 328 #endif
 329
 330         post_cache_as_ram(cpu_reset);
 331
 332 }