2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FAILOVER_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
10 default ROM_SECTION_SIZE = FALLBACK_SIZE
11 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
13 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
14 default ROM_SECTION_OFFSET = 0
19 ## Compute the start location and size size of
20 ## The linuxBIOS bootloader.
22 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
23 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
26 ## Compute where this copy of linuxBIOS will start in the boot rom
28 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
31 ## Compute a range of ROM that can cached to speed up linuxBIOS,
34 ## XIP_ROM_SIZE must be a power of 2.
35 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
37 default XIP_ROM_SIZE=65536
40 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
43 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
45 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
52 ## Build the objects we have code for in this directory.
59 #needed by irq_tables and mptable and acpi_tables
71 # object acpi_tables.o
73 # if SB_HT_CHAIN_ON_BUS0
80 # if SB_HT_CHAIN_ON_BUS0
92 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
93 action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
94 action "mv dsdt_lb.hex dsdt.c"
98 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
102 depends "$(MAINBOARD)/dx/pci2.asl"
103 action "iasl -tc $(MAINBOARD)/dx/pci2.asl"
104 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
105 action "mv pci2.hex ssdt2.c"
114 # compile cache_as_ram.c to auto.o
115 makerule ./cache_as_ram_auto.o
116 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
117 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
121 #compile cache_as_ram.c to auto.inc
122 makerule ./cache_as_ram_auto.inc
123 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
124 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
125 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
126 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
135 makerule ./failover.E
136 depends "$(MAINBOARD)/failover.c ./romcc"
137 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
140 makerule ./failover.inc
141 depends "$(MAINBOARD)/failover.c ./romcc"
142 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
146 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
147 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
150 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
151 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
156 ## Build our 16 bit and 32 bit linuxBIOS entry code
158 if HAVE_FAILOVER_BOOT
159 if USE_FAILOVER_IMAGE
160 mainboardinit cpu/x86/16bit/entry16.inc
161 ldscript /cpu/x86/16bit/entry16.lds
164 if USE_FALLBACK_IMAGE
165 mainboardinit cpu/x86/16bit/entry16.inc
166 ldscript /cpu/x86/16bit/entry16.lds
170 mainboardinit cpu/x86/32bit/entry32.inc
173 ldscript /cpu/x86/32bit/entry32.lds
177 ldscript /cpu/amd/car/cache_as_ram.lds
182 ## Build our reset vector (This is where linuxBIOS is entered)
184 if HAVE_FAILOVER_BOOT
185 if USE_FAILOVER_IMAGE
186 mainboardinit cpu/x86/16bit/reset16.inc
187 ldscript /cpu/x86/16bit/reset16.lds
189 mainboardinit cpu/x86/32bit/reset32.inc
190 ldscript /cpu/x86/32bit/reset32.lds
193 if USE_FALLBACK_IMAGE
194 mainboardinit cpu/x86/16bit/reset16.inc
195 ldscript /cpu/x86/16bit/reset16.lds
197 mainboardinit cpu/x86/32bit/reset32.inc
198 ldscript /cpu/x86/32bit/reset32.lds
204 ### Should this be in the northbridge code?
205 mainboardinit arch/i386/lib/cpu_reset.inc
209 ## Include an id string (For safe flashing)
211 mainboardinit arch/i386/lib/id.inc
212 ldscript /arch/i386/lib/id.lds
216 ## Setup Cache-As-Ram
218 mainboardinit cpu/amd/car/cache_as_ram.inc
222 ### This is the early phase of linuxBIOS startup
223 ### Things are delicate and we test to see if we should
224 ### failover to another image.
226 if HAVE_FAILOVER_BOOT
227 if USE_FAILOVER_IMAGE
229 ldscript /arch/i386/lib/failover_failover.lds
233 if USE_FALLBACK_IMAGE
235 ldscript /arch/i386/lib/failover.lds
237 ldscript /arch/i386/lib/failover.lds
238 mainboardinit ./failover.inc
244 ### O.k. We aren't just an intermediary anymore!
253 initobject cache_as_ram_auto.o
255 mainboardinit ./cache_as_ram_auto.inc
263 mainboardinit cpu/x86/fpu/enable_fpu.inc
264 mainboardinit cpu/x86/mmx/enable_mmx.inc
265 mainboardinit cpu/x86/sse/enable_sse.inc
266 mainboardinit ./auto.inc
267 mainboardinit cpu/x86/sse/disable_sse.inc
268 mainboardinit cpu/x86/mmx/disable_mmx.inc
273 ## Include the secondary Configuration files
279 # sample config for amd/serengeti_cheetah
280 chip northbridge/amd/amdk8/root_complex
281 device apic_cluster 0 on
282 chip cpu/amd/socket_940
286 device pci_domain 0 on
287 chip northbridge/amd/amdk8
288 device pci 18.0 on # northbridge
289 # devices on link 0, link 0 == LDT 0
290 chip southbridge/amd/amd8132
291 # the on/off keyword is mandatory
292 device pci 0.0 on end
293 device pci 0.1 on end
294 device pci 1.0 on end
295 device pci 1.1 on end
297 chip southbridge/amd/amd8111
298 # this "device pci 0.0" is the parent the next one
301 device pci 0.0 on end
302 device pci 0.1 on end
303 device pci 0.2 off end
304 device pci 1.0 off end
307 chip superio/winbond/w83627hf
308 device pnp 2e.0 off # Floppy
313 device pnp 2e.1 off # Parallel Port
317 device pnp 2e.2 on # Com1
321 device pnp 2e.3 off # Com2
325 device pnp 2e.5 on # Keyboard
331 device pnp 2e.6 off # CIR
334 device pnp 2e.7 off # GAME_MIDI_GIPO1
339 device pnp 2e.8 off end # GPIO2
340 device pnp 2e.9 off end # GPIO3
341 device pnp 2e.a off end # ACPI
342 device pnp 2e.b on # HW Monitor
348 device pci 1.1 on end
349 device pci 1.2 on end
351 chip drivers/i2c/i2cmux # pca9556 smbus mux
352 device i2c 18 on #0 pca9516 1
353 chip drivers/generic/generic #dimm 0-0-0
356 chip drivers/generic/generic #dimm 0-0-1
359 chip drivers/generic/generic #dimm 0-1-0
362 chip drivers/generic/generic #dimm 0-1-1
366 device i2c 18 on #1 pca9516 2
367 chip drivers/generic/generic #dimm 1-0-0
370 chip drivers/generic/generic #dimm 1-0-1
373 chip drivers/generic/generic #dimm 1-1-0
376 chip drivers/generic/generic #dimm 1-1-1
382 device pci 1.5 off end
383 device pci 1.6 off end
384 register "ide0_enable" = "1"
385 register "ide1_enable" = "1"
387 end # device pci 18.0
389 device pci 18.0 on end
390 device pci 18.0 on end
391 device pci 18.1 on end
392 device pci 18.2 on end
393 device pci 18.3 on end
395 chip northbridge/amd/amdk8
396 device pci 19.0 on # northbridge
397 chip southbridge/amd/amd8151
398 # the on/off keyword is mandatory
399 device pci 0.0 on end
400 device pci 1.0 on end
402 end # device pci 19.0
404 device pci 19.0 on end
405 device pci 19.0 on end
406 device pci 19.1 on end
407 device pci 19.2 on end
408 device pci 19.3 on end
413 # chip drivers/generic/debug
414 # device pnp 0.0 off end # chip name
415 # device pnp 0.1 on end # pci_regs_all
416 # device pnp 0.2 off end # mem
417 # device pnp 0.3 off end # cpuid
418 # device pnp 0.4 off end # smbus_regs_all
419 # device pnp 0.5 off end # dual core msr
420 # device pnp 0.6 off end # cache size
421 # device pnp 0.7 off end # tsc