2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #define SYSTEM_TYPE 0 /* SERVER */
25 //#define SYSTEM_TYPE 1 /* DESKTOP */
26 //#define SYSTEM_TYPE 2 /* MOBILE */
29 #define RAMINIT_SYSINFO 1
30 #define CACHE_AS_RAM_ADDRESS_DEBUG 1
34 #define SET_NB_CFG_54 1
37 #define QRANK_DIMM_SUPPORT 1
39 //used by incoherent_ht
40 #define FAM10_SCAN_PCI_BUS 0
41 #define FAM10_ALLOCATE_IO_RANGE 0
43 //used by init_cpus and fidvid
44 #define FAM10_SET_FIDVID 1
45 #define FAM10_SET_FIDVID_CORE_RANGE 0
49 #include <device/pci_def.h>
50 #include <device/pci_ids.h>
52 #include <device/pnp_def.h>
53 #include <arch/romcc_io.h>
54 #include <cpu/x86/lapic.h>
55 #include "option_table.h"
56 #include "pc80/mc146818rtc_early.c"
58 /* FIXME: Use console.c post_code function */
59 static void post_code(u8 value) {
63 #if (CONFIG_USE_FAILOVER_IMAGE == 0)
64 #include "arch/i386/lib/console.c"
65 #include "pc80/serial.c"
66 #include "lib/ramtest.c"
67 #include <cpu/amd/model_10xxx_rev.h>
68 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
69 #include "northbridge/amd/amdfam10/raminit.h"
70 #include "northbridge/amd/amdfam10/amdfam10.h"
73 #include "cpu/x86/lapic/boot_cpu.c"
74 #include "northbridge/amd/amdfam10/reset_test.c"
76 #include <console/loglevel.h>
78 void die(const char *msg);
79 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
80 #define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
82 #include "cpu/x86/bist.h"
85 #if (CONFIG_USE_FAILOVER_IMAGE == 0)
87 #include "northbridge/amd/amdfam10/debug.c"
88 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
89 #include "cpu/amd/mtrr/amd_earlymtrr.c"
90 #include "northbridge/amd/amdfam10/setup_resource_map.c"
92 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
93 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
95 static void memreset_setup(void)
97 //GPIO on amd8111 to enable MEMRST ????
98 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
99 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
103 static void memreset(int controllers, const struct mem_controller *ctrl)
108 static void activate_spd_rom(const struct mem_controller *ctrl)
110 #define SMBUS_HUB 0x18
112 u8 device = ctrl->spd_switch_addr;
114 printk_debug("switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
116 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
119 ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
120 } while ((ret!=0) && (i-->0));
121 smbus_write_byte(SMBUS_HUB, 0x03, 0);
125 static int spd_read_byte(u32 device, u32 address)
128 result = smbus_read_byte(device, address);
132 #include "northbridge/amd/amdfam10/amdfam10.h"
133 #include "northbridge/amd/amdht/ht_wrapper.c"
135 #include "include/cpu/x86/mem.h"
136 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
137 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
138 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
140 #include "resourcemap.c"
141 #include "cpu/amd/quadcore/quadcore.c"
142 #include "cpu/amd/car/copy_and_run.c"
143 #include "cpu/amd/car/post_cache_as_ram.c"
144 #include "cpu/amd/model_10xxx/init_cpus.c"
145 #include "cpu/amd/model_10xxx/fidvid.c"
147 #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
150 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
151 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
152 #include "northbridge/amd/amdfam10/early_ht.c"
154 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
156 int last_boot_normal_flag = last_boot_normal();
158 /* Is this a cpu only reset? or Is this a secondary cpu? */
159 if ((cpu_init_detectedx) || (!boot_cpu())) {
160 if (last_boot_normal_flag) {
167 /* Nothing special needs to be done to find bus 0 */
168 /* Allow the HT devices to be found */
169 /* mov bsp to bus 0xff when > 8 nodes */
170 set_bsp_node_CHtExtNodeCfgEn();
171 enumerate_ht_chain();
173 /* Setup the rom access for 4M */
174 amd8111_enable_rom();
176 /* Is this a deliberate reset by the bios */
177 if (bios_reset_detected() && last_boot_normal_flag) {
180 /* This is the primary cpu how should I boot? */
181 else if (do_normal_boot()) {
189 __asm__ volatile ("jmp __normal_image"
191 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
195 #if CONFIG_HAVE_FAILOVER_BOOT==1
196 __asm__ volatile ("jmp __fallback_image"
198 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
203 #endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */
206 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
208 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
210 //FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0.
211 #if CONFIG_HAVE_FAILOVER_BOOT==1
212 #if CONFIG_USE_FAILOVER_IMAGE==1
213 failover_process(bist, cpu_init_detectedx);
215 real_main(bist, cpu_init_detectedx);
218 #if CONFIG_USE_FALLBACK_IMAGE == 1
219 failover_process(bist, cpu_init_detectedx);
221 real_main(bist, cpu_init_detectedx);
226 #if (CONFIG_USE_FAILOVER_IMAGE==0)
227 #include "spd_addr.h"
228 #include "cpu/amd/microcode/microcode.c"
229 #include "cpu/amd/model_10xxx/update_microcode.c"
231 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
234 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
242 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
243 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
248 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
253 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
255 /* Halt if there was a built in self test failure */
256 report_bist_failure(bist);
260 printk_debug("BSP Family_Model: %08x \n", val);
261 printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
262 printk_debug("bsp_apicid = %02x \n", bsp_apicid);
263 printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
265 /* Setup sysinfo defaults */
266 set_sysinfo_in_ram(0);
268 update_microcode(val);
274 amd_ht_init(sysinfo);
277 /* Setup nodes PCI space and start core 0 AP init. */
278 finalize_node_setup(sysinfo);
280 /* Setup any mainboard PCI settings etc. */
281 setup_mb_resource_map();
284 /* wait for all the APs core0 started by finalize_node_setup. */
285 /* FIXME: A bunch of cores are going to start output to serial at once.
286 It would be nice to fixup prink spinlocks for ROM XIP mode.
287 I think it could be done by putting the spinlock flag in the cache
288 of the BSP located right after sysinfo.
290 wait_all_core0_started();
292 #if CONFIG_LOGICAL_CPUS==1
293 /* Core0 on each node is configured. Now setup any additional cores. */
294 printk_debug("start_other_cores()\n");
297 wait_all_other_cores_started(bsp_apicid);
302 #if FAM10_SET_FIDVID == 1
303 msr = rdmsr(0xc0010071);
304 printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
306 /* FIXME: The sb fid change may survive the warm reset and only
307 need to be done once.*/
308 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
312 if (!warm_reset_detect(0)) { // BSP is node 0
313 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
315 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
320 /* show final fid and vid */
321 msr=rdmsr(0xc0010071);
322 printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
326 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
327 if (!warm_reset_detect(0)) {
328 print_info("...WARM RESET...\n\n\n");
329 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
330 die("After soft_reset_x - shouldn't see this message!!!\n");
336 /* FIXME: Move this to chipset init.
337 enable cf9 for hard reset */
338 print_debug("enable_cf9_x()\n");
339 enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
342 /* It's the time to set ctrl in sysinfo now; */
343 printk_debug("fill_mem_ctrl()\n");
344 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
348 printk_debug("enable_smbus()\n");
356 // die("Die Before MCT init.");
358 printk_debug("raminit_amdmct()\n");
359 raminit_amdmct(sysinfo);
364 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
365 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
366 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
367 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
370 // ram_check(0x00200000, 0x00200000 + (640 * 1024));
371 // ram_check(0x40200000, 0x40200000 + (640 * 1024));
374 // die("After MCT init before CAR disabled.");
377 printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
378 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
379 post_code(0x43); // Should never see this post code.
385 #endif /* CONFIG_USE_FAILOVER_IMAGE==0 */