2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <device/pci.h>
25 #if CONFIG_LOGICAL_CPUS==1
26 #include <cpu/amd/multicore.h>
29 #include <cpu/amd/amdfam10_sysconf.h>
30 #include "mb_sysconf.h"
34 static void *smp_write_config_table(void *v)
36 static const char sig[4] = "PCMP";
37 static const char oem[8] = "COREBOOT";
38 static const char productid[12] = "SERENGETI ";
39 struct mp_config_table *mc;
43 struct mb_sysconf_t *m;
45 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 memset(mc, 0, sizeof(*mc));
48 memcpy(mc->mpc_signature, sig, sizeof(sig));
49 mc->mpc_length = sizeof(*mc); /* initially just the header */
51 mc->mpc_checksum = 0; /* not yet computed */
52 memcpy(mc->mpc_oem, oem, sizeof(oem));
53 memcpy(mc->mpc_productid, productid, sizeof(productid));
56 mc->mpc_entry_count = 0; /* No entries yet... */
57 mc->mpc_lapic = LAPIC_ADDR;
62 smp_write_processors(mc);
69 /* define bus and isa numbers */
70 for(j= 0; j < 256 ; j++) {
72 smp_write_bus(mc, j, "PCI ");
74 smp_write_bus(mc, m->bus_isa, "ISA ");
76 /*I/O APICs: APIC ID Version State Address*/
77 smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
81 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
83 res = find_resource(dev, PCI_BASE_ADDRESS_0);
85 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
88 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
90 res = find_resource(dev, PCI_BASE_ADDRESS_0);
92 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
98 for(i=1; i< sysconf.hc_possible_num; i++) {
99 if(!(sysconf.pci1234[i] & 0x1) ) continue;
101 switch(sysconf.hcid[i]) {
104 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
106 res = find_resource(dev, PCI_BASE_ADDRESS_0);
108 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
111 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
113 res = find_resource(dev, PCI_BASE_ADDRESS_0);
115 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
125 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
126 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1);
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_8111, 0x3);
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_8111, 0x4);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_8111, 0x5);
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_8111, 0x6);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_8111, 0x7);
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_8111, 0x8);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_8111, 0x9);
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_8111, 0xc);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_8111, 0xd);
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_8111, 0xe);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_8111, 0xf);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
158 // Slot 1 PCI-X 133/100/66
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
164 //Slot 2 PCI-X 133/100/66
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
171 for(i=1; i< sysconf.hc_possible_num; i++) {
172 if(!(sysconf.pci1234[i] & 0x1) ) continue;
176 struct resource *res;
177 switch(sysconf.hcid[i]) {
180 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
182 res = find_resource(dev, PCI_BASE_ADDRESS_0);
184 for(jj=0; jj<4; jj++) {
185 //Slot 1 PCI-X 133/100/66
186 for(ii=0;ii<4;ii++) {
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
193 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
195 res = find_resource(dev, PCI_BASE_ADDRESS_0);
197 for(jj=0; jj<4; jj++) {
198 //Slot 2 PCI-X 133/100/66
199 for(ii=0;ii<4;ii++) {
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
210 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
219 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
220 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
221 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
222 /* There is no extension information... */
224 /* Compute the checksums */
225 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
226 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
227 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
228 mc, smp_next_mpe_entry(mc));
229 return smp_next_mpe_entry(mc);
232 unsigned long write_smp_table(unsigned long addr)
235 v = smp_write_floating_table(addr);
236 return (unsigned long)smp_write_config_table(v);